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authorsaurabhb172019-07-02 17:08:16 +0530
committerGitHub2019-07-02 17:08:16 +0530
commit83d93769478a1805083666479d4ff83b875ba955 (patch)
treed97a2f3543ab4e5164490495ee19f20352ecb71f /src/SubcircuitLibrary/full_sub/full_sub.sub
parent29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (diff)
parent8c44f97b533607d057a28e029e42f001270f4fd4 (diff)
downloadeSim-83d93769478a1805083666479d4ff83b875ba955.tar.gz
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Merge pull request #115 from nilshah98/ese
Adding the work done by FSF 2019 eSim ECE Fellows
Diffstat (limited to 'src/SubcircuitLibrary/full_sub/full_sub.sub')
-rw-r--r--src/SubcircuitLibrary/full_sub/full_sub.sub13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub
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+* Subcircuit full_sub
+.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_
+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
+.include half_sub.sub
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
+x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
+x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
+a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends full_sub \ No newline at end of file