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| author | fossee | 2019-08-29 12:03:11 +0530 |
|---|---|---|
| committer | fossee | 2019-08-29 12:03:11 +0530 |
| commit | fe3bd934634bb2dae1cadf35e7c6d59facbedf66 (patch) | |
| tree | ab841ad9ca3d56f7eb85cb3650f6608b80656027 /src/SubcircuitLibrary/full_adder/half_adder.sub | |
| parent | f7567ac99f21fb6c87d60f309f0aa71dee6ae975 (diff) | |
| download | eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.tar.gz eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.tar.bz2 eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.zip | |
adding files
Diffstat (limited to 'src/SubcircuitLibrary/full_adder/half_adder.sub')
| -rw-r--r-- | src/SubcircuitLibrary/full_adder/half_adder.sub | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sub b/src/SubcircuitLibrary/full_adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
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