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| author | fahim | 2015-07-28 14:16:32 +0530 |
|---|---|---|
| committer | fahim | 2015-07-28 14:16:32 +0530 |
| commit | 7cdabba6ca27643fc290c6fada8c8fa333e7f8fb (patch) | |
| tree | 38c1cb7101ccb2e1b88861c3a4f1939703ece88f /src/SubcircuitLibrary/full_adder/full_adder.cir | |
| parent | 1c21a0ad49a75671a9fd775463ab6e6e6f3a8e36 (diff) | |
| download | eSim-7cdabba6ca27643fc290c6fada8c8fa333e7f8fb.tar.gz eSim-7cdabba6ca27643fc290c6fada8c8fa333e7f8fb.tar.bz2 eSim-7cdabba6ca27643fc290c6fada8c8fa333e7f8fb.zip | |
Subject: Added subcircuit for Half Adder and Full Adder.
Description: Added subcircuit for Half Adder and Full Adder.
Diffstat (limited to 'src/SubcircuitLibrary/full_adder/full_adder.cir')
| -rw-r--r-- | src/SubcircuitLibrary/full_adder/full_adder.cir | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir b/src/SubcircuitLibrary/full_adder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end |