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| author | fahim | 2015-07-28 14:16:32 +0530 |
|---|---|---|
| committer | fahim | 2015-07-28 14:16:32 +0530 |
| commit | 7cdabba6ca27643fc290c6fada8c8fa333e7f8fb (patch) | |
| tree | 38c1cb7101ccb2e1b88861c3a4f1939703ece88f /src/SubcircuitLibrary/full_adder/full_adder.cir.out | |
| parent | 1c21a0ad49a75671a9fd775463ab6e6e6f3a8e36 (diff) | |
| download | eSim-7cdabba6ca27643fc290c6fada8c8fa333e7f8fb.tar.gz eSim-7cdabba6ca27643fc290c6fada8c8fa333e7f8fb.tar.bz2 eSim-7cdabba6ca27643fc290c6fada8c8fa333e7f8fb.zip | |
Subject: Added subcircuit for Half Adder and Full Adder.
Description: Added subcircuit for Half Adder and Full Adder.
Diffstat (limited to 'src/SubcircuitLibrary/full_adder/full_adder.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/full_adder/full_adder.cir.out | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir.out b/src/SubcircuitLibrary/full_adder/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |