remove temporary files

5 files changed, 0 insertions, 256 deletions

diff --git a/src/SubcircuitLibrary/diac/diac-cache.lib b/src/SubcircuitLibrary/diac/diac-cache.lib
deleted file mode 100644
index b15fdeec..00000000
--- a/src/SubcircuitLibrary/diac/diac-cache.lib
+++ /dev/null
@@ -1,67 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# GND
-#
-DEF GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "GND" 0 -150 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 6 0 1 0  0 0  0 -50  50 -50  0 -100  -50 -50  0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
-ENDDRAW
-ENDDEF
-#
-# aswitch
-#
-DEF aswitch U 0 40 Y Y 1 F N
-F0 "U" 450 300 60 H V C CNN
-F1 "aswitch" 450 200 60 H V C CNN
-F2 "" 450 100 60 H V C CNN
-F3 "" 450 100 60 H V C CNN
-DRAW
-S 200 250 650 100 0 1 0 N
-X ~ 2 0 150 200 R 50 50 1 1 O
-X ~ 3 850 150 200 L 50 50 1 1 O
-X ~ 1_IN 450 -100 200 U 50 20 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/diac/diac.bak b/src/SubcircuitLibrary/diac/diac.bak
deleted file mode 100644
index 16009984..00000000
--- a/src/SubcircuitLibrary/diac/diac.bak
+++ /dev/null
@@ -1,138 +0,0 @@
-EESchema Schematic File Version 2  date 09/22/14 16:36:31

-LIBS:power

-LIBS:device

-LIBS:transistors

-LIBS:conn

-LIBS:linear

-LIBS:regul

-LIBS:74xx

-LIBS:cmos4000

-LIBS:adc-dac

-LIBS:memory

-LIBS:xilinx

-LIBS:special

-LIBS:microcontrollers

-LIBS:dsp

-LIBS:microchip

-LIBS:analog_switches

-LIBS:motorola

-LIBS:texas

-LIBS:intel

-LIBS:audio

-LIBS:interface

-LIBS:digital-audio

-LIBS:philips

-LIBS:display

-LIBS:cypress

-LIBS:siliconi

-LIBS:opto

-LIBS:atmel

-LIBS:contrib

-LIBS:valves

-LIBS:analogSpice

-LIBS:analogXSpice

-LIBS:convergenceAidSpice

-LIBS:converterSpice

-LIBS:digitalSpice

-LIBS:digitalXSpice

-LIBS:linearSpice

-LIBS:measurementSpice

-LIBS:portSpice

-LIBS:sourcesSpice

-LIBS:diac-cache

-EELAYER 25  0

-EELAYER END

-$Descr A4 11700 8267

-encoding utf-8

-Sheet 1 1

-Title ""

-Date "22 sep 2014"

-Rev ""

-Comp ""

-Comment1 ""

-Comment2 ""

-Comment3 ""

-Comment4 ""

-$EndDescr

-Wire Wire Line

-	4150 2750 4150 3450

-Connection ~ 4400 3750

-Wire Wire Line

-	4900 4250 4900 4450

-Wire Wire Line

-	4900 4450 4400 4450

-Wire Wire Line

-	4400 4450 4400 3450

-Wire Wire Line

-	5200 3400 5200 4050

-Connection ~ 4600 3400

-Wire Wire Line

-	4600 4050 4600 2750

-Wire Wire Line

-	4600 2750 4150 2750

-Wire Wire Line

-	4150 3250 4150 3600

-Wire Wire Line

-	4400 3450 4150 3450

-Connection ~ 4150 3450

-Wire Wire Line

-	4400 3750 4900 3750

-Wire Wire Line

-	4900 3750 4900 3600

-Wire Wire Line

-	4150 4100 4150 4300

-$Comp

-L PWR_FLAG #FLG01

-U 1 1 5417D647

-P 4150 4300

-F 0 "#FLG01" H 4150 4570 30  0001 C CNN

-F 1 "PWR_FLAG" H 4150 4530 30  0000 C CNN

-	1    4150 4300

-	0    1    1    0   

-$EndComp

-$Comp

-L PORT U3

-U 2 1 5417D62C

-P 5450 3400

-F 0 "U3" H 5450 3350 30  0000 C CNN

-F 1 "PORT" H 5450 3400 30  0000 C CNN

-	2    5450 3400

-	-1   0    0    1   

-$EndComp

-$Comp

-L PORT U3

-U 1 1 5417D624

-P 4150 2500

-F 0 "U3" H 4150 2450 30  0000 C CNN

-F 1 "PORT" H 4150 2500 30  0000 C CNN

-	1    4150 2500

-	0    1    1    0   

-$EndComp

-$Comp

-L GND #PWR02

-U 1 1 5417D5DC

-P 4150 4300

-F 0 "#PWR02" H 4150 4300 30  0001 C CNN

-F 1 "GND" H 4150 4230 30  0001 C CNN

-	1    4150 4300

-	1    0    0    -1  

-$EndComp

-$Comp

-L ANALOGSWITCH U2

-U 1 1 5417D537

-P 4900 4050

-F 0 "U2" H 4700 4100 30  0000 C CNN

-F 1 "ANALOGSWITCH" H 4900 4050 30  0000 C CNN

-	1    4900 4050

-	1    0    0    -1  

-$EndComp

-$Comp

-L ANALOGSWITCH U1

-U 1 1 5417D530

-P 4900 3400

-F 0 "U1" H 4700 3450 30  0000 C CNN

-F 1 "ANALOGSWITCH" H 4900 3400 30  0000 C CNN

-	1    4900 3400

-	1    0    0    -1  

-$EndComp

-$EndSCHEMATC

diff --git a/src/SubcircuitLibrary/diac/diac.cir.ckt b/src/SubcircuitLibrary/diac/diac.cir.ckt
deleted file mode 100644
index e89f9cfb..00000000
--- a/src/SubcircuitLibrary/diac/diac.cir.ckt
+++ /dev/null
@@ -1,9 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 09/22/14 16:36:23

-

-u3  1 2 port

-* Analog Switch analogswitch

-* Analog Switch analogswitch

-a1 1 (1 2) u2

-.model u2 aswitch(cntl_on=-25 cntl_off=-0.1 r_on=0.0125 r_off=1000000)

-a2 1 (1 2) u1

-.model u1 aswitch(cntl_on=25 cntl_off=0.1 r_on=0.0125 r_off=1000000)

diff --git a/src/SubcircuitLibrary/diac/diac.cir.out~ b/src/SubcircuitLibrary/diac/diac.cir.out~
deleted file mode 100644
index 89cc8142..00000000
--- a/src/SubcircuitLibrary/diac/diac.cir.out~
+++ /dev/null
@@ -1,24 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-
-* u3  1 2 port
-* u1  1 1 2 aswitch
-* u2  1 1 2 aswitch
-a1 1 [1 2 ] u1
-a2 1 [1 2 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/diac/diac.sub~ b/src/SubcircuitLibrary/diac/diac.sub~
deleted file mode 100644
index 43c2d279..00000000
--- a/src/SubcircuitLibrary/diac/diac.sub~
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit diac
-.subckt diac 1 2 
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-* u1  1 1 2 aswitch
-* u2  1 1 2 aswitch
-a1 1 [1 2 ] u1
-a2 1 [1 2 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Control Statements
-
-.ends diac
\ No newline at end of file