diff options
author | saurabhb17 | 2019-07-02 17:08:16 +0530 |
---|---|---|
committer | GitHub | 2019-07-02 17:08:16 +0530 |
commit | 83d93769478a1805083666479d4ff83b875ba955 (patch) | |
tree | d97a2f3543ab4e5164490495ee19f20352ecb71f /src/SubcircuitLibrary/LOGIC_ADDER | |
parent | 29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (diff) | |
parent | 8c44f97b533607d057a28e029e42f001270f4fd4 (diff) | |
download | eSim-83d93769478a1805083666479d4ff83b875ba955.tar.gz eSim-83d93769478a1805083666479d4ff83b875ba955.tar.bz2 eSim-83d93769478a1805083666479d4ff83b875ba955.zip |
Merge pull request #115 from nilshah98/ese
Adding the work done by FSF 2019 eSim ECE Fellows
Diffstat (limited to 'src/SubcircuitLibrary/LOGIC_ADDER')
8 files changed, 447 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib new file mode 100644 index 00000000..34588988 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir new file mode 100644 index 00000000..ec177d39 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir @@ -0,0 +1,16 @@ +* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 A B Net-_U2-Pad3_ d_and
+U4 Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and
+U3 A B Net-_U3-Pad3_ d_xor
+U5 Net-_U3-Pad3_ CIN SUM d_xor
+U6 Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or
+U1 A B CIN SUM CARRY PORT
+
+.end
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out new file mode 100644 index 00000000..df9bcde6 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out @@ -0,0 +1,32 @@ +* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
+
+* u2 a b net-_u2-pad3_ d_and
+* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
+* u3 a b net-_u3-pad3_ d_xor
+* u5 net-_u3-pad3_ cin sum d_xor
+* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
+* u1 a b cin sum carry port
+a1 [a b ] net-_u2-pad3_ u2
+a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
+a3 [a b ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ cin ] sum u5
+a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 10e-03 100e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro new file mode 100644 index 00000000..a2b9fa1f --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro @@ -0,0 +1,44 @@ +update=Sat Jun 8 13:01:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch new file mode 100644 index 00000000..d39a1b78 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:LOGIC_ADDER-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5AB647D1
+P 4100 2200
+F 0 "U2" H 4100 2200 60 0000 C CNN
+F 1 "d_and" H 4150 2300 60 0000 C CNN
+F 2 "" H 4100 2200 60 0000 C CNN
+F 3 "" H 4100 2200 60 0000 C CNN
+ 1 4100 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 5AB648AD
+P 5250 2300
+F 0 "U4" H 5250 2300 60 0000 C CNN
+F 1 "d_and" H 5300 2400 60 0000 C CNN
+F 2 "" H 5250 2300 60 0000 C CNN
+F 3 "" H 5250 2300 60 0000 C CNN
+ 1 5250 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U3
+U 1 1 5AB648E7
+P 4100 2750
+F 0 "U3" H 4100 2750 60 0000 C CNN
+F 1 "d_xor" H 4150 2850 47 0000 C CNN
+F 2 "" H 4100 2750 60 0000 C CNN
+F 3 "" H 4100 2750 60 0000 C CNN
+ 1 4100 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U5
+U 1 1 5AB6498F
+P 5250 2600
+F 0 "U5" H 5250 2600 60 0000 C CNN
+F 1 "d_xor" H 5300 2700 47 0000 C CNN
+F 2 "" H 5250 2600 60 0000 C CNN
+F 3 "" H 5250 2600 60 0000 C CNN
+ 1 5250 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U6
+U 1 1 5AB64A11
+P 6250 2250
+F 0 "U6" H 6250 2250 60 0000 C CNN
+F 1 "d_or" H 6250 2350 60 0000 C CNN
+F 2 "" H 6250 2250 60 0000 C CNN
+F 3 "" H 6250 2250 60 0000 C CNN
+ 1 6250 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5AB64A78
+P 2650 2100
+F 0 "U1" H 2700 2200 30 0000 C CNN
+F 1 "PORT" H 2650 2100 30 0000 C CNN
+F 2 "" H 2650 2100 60 0000 C CNN
+F 3 "" H 2650 2100 60 0000 C CNN
+ 1 2650 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5AB64BE9
+P 2650 2300
+F 0 "U1" H 2700 2400 30 0000 C CNN
+F 1 "PORT" H 2650 2300 30 0000 C CNN
+F 2 "" H 2650 2300 60 0000 C CNN
+F 3 "" H 2650 2300 60 0000 C CNN
+ 2 2650 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5AB64C18
+P 6300 2550
+F 0 "U1" H 6350 2650 30 0000 C CNN
+F 1 "PORT" H 6300 2550 30 0000 C CNN
+F 2 "" H 6300 2550 60 0000 C CNN
+F 3 "" H 6300 2550 60 0000 C CNN
+ 4 6300 2550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5AB64C59
+P 2650 2900
+F 0 "U1" H 2700 3000 30 0000 C CNN
+F 1 "PORT" H 2650 2900 30 0000 C CNN
+F 2 "" H 2650 2900 60 0000 C CNN
+F 3 "" H 2650 2900 60 0000 C CNN
+ 3 2650 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5AB64C94
+P 7150 2200
+F 0 "U1" H 7200 2300 30 0000 C CNN
+F 1 "PORT" H 7150 2200 30 0000 C CNN
+F 2 "" H 7150 2200 60 0000 C CNN
+F 3 "" H 7150 2200 60 0000 C CNN
+ 5 7150 2200
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 2900 2100 3650 2100
+Wire Wire Line
+ 2900 2250 3650 2250
+Wire Wire Line
+ 3650 2250 3650 2200
+Wire Wire Line
+ 3400 2100 3400 2650
+Wire Wire Line
+ 3400 2650 3650 2650
+Connection ~ 3400 2100
+Wire Wire Line
+ 3150 2250 3150 2750
+Wire Wire Line
+ 3150 2750 3650 2750
+Connection ~ 3150 2250
+Wire Wire Line
+ 4550 2700 4550 2500
+Wire Wire Line
+ 4550 2500 4800 2500
+Wire Wire Line
+ 2900 2900 4800 2900
+Wire Wire Line
+ 4800 2900 4800 2600
+Wire Wire Line
+ 4700 2500 4700 2200
+Wire Wire Line
+ 4700 2200 4800 2200
+Connection ~ 4700 2500
+Wire Wire Line
+ 4800 2300 4600 2300
+Wire Wire Line
+ 4600 2300 4600 2900
+Connection ~ 4600 2900
+Wire Wire Line
+ 5700 2250 5800 2250
+Wire Wire Line
+ 4550 2150 4550 2000
+Wire Wire Line
+ 4550 2000 5800 2000
+Wire Wire Line
+ 5800 2000 5800 2150
+Wire Wire Line
+ 5700 2550 6050 2550
+Wire Wire Line
+ 6700 2200 6900 2200
+Wire Wire Line
+ 2900 2250 2900 2300
+Text GLabel 3000 1850 0 60 Input ~ 0
+A
+Text GLabel 3000 2500 0 60 Input ~ 0
+B
+Text GLabel 3000 3250 0 60 Input ~ 0
+CIN
+Wire Wire Line
+ 3000 3250 3050 3250
+Wire Wire Line
+ 3050 3250 3050 2900
+Connection ~ 3050 2900
+Wire Wire Line
+ 3000 1850 3100 1850
+Wire Wire Line
+ 3100 1850 3100 2100
+Connection ~ 3100 2100
+Wire Wire Line
+ 3000 2500 3000 2250
+Connection ~ 3000 2250
+Text GLabel 6750 1700 0 60 Output ~ 0
+CARRY
+Text GLabel 5950 2800 0 60 Output ~ 0
+SUM
+Wire Wire Line
+ 6750 1700 6800 1700
+Wire Wire Line
+ 6800 1700 6800 2200
+Connection ~ 6800 2200
+Wire Wire Line
+ 5950 2550 5950 2800
+Connection ~ 5950 2550
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub new file mode 100644 index 00000000..a1e1cfac --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub @@ -0,0 +1,26 @@ +* Subcircuit LOGIC_ADDER
+.subckt LOGIC_ADDER a b cin sum carry
+* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
+* u2 a b net-_u2-pad3_ d_and
+* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
+* u3 a b net-_u3-pad3_ d_xor
+* u5 net-_u3-pad3_ cin sum d_xor
+* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
+a1 [a b ] net-_u2-pad3_ u2
+a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
+a3 [a b ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ cin ] sum u5
+a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends LOGIC_ADDER
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml new file mode 100644 index 00000000..ab59f216 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/analysis b/src/SubcircuitLibrary/LOGIC_ADDER/analysis new file mode 100644 index 00000000..d5e13546 --- /dev/null +++ b/src/SubcircuitLibrary/LOGIC_ADDER/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-00
\ No newline at end of file |