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authorsaurabhb172019-07-02 17:08:16 +0530
committerGitHub2019-07-02 17:08:16 +0530
commit83d93769478a1805083666479d4ff83b875ba955 (patch)
treed97a2f3543ab4e5164490495ee19f20352ecb71f /src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir
parent29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (diff)
parent8c44f97b533607d057a28e029e42f001270f4fd4 (diff)
downloadeSim-83d93769478a1805083666479d4ff83b875ba955.tar.gz
eSim-83d93769478a1805083666479d4ff83b875ba955.tar.bz2
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Merge pull request #115 from nilshah98/ese
Adding the work done by FSF 2019 eSim ECE Fellows
Diffstat (limited to 'src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir')
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+* C:\eSim\eSim\src\SubcircuitLibrary\MUX\MUX.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:29:10 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and
+U4 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and
+U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad4_ d_or
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end