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| author | Rahul P | 2020-03-04 17:01:11 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-04 17:01:11 +0530 |
| commit | 8ffe81b36caa259151978de0434e4e0c5c32d217 (patch) | |
| tree | 32202454d13dfabbf6556e98987f2a9632619ea9 /src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub | |
| parent | e40317e709c220176fc5b7edf23d4434504335b0 (diff) | |
| parent | 13f3bcfda9416624cebbf5705de398e8efcad344 (diff) | |
| download | eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2 eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.zip | |
Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub')
| -rw-r--r-- | src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub deleted file mode 100644 index a1e1cfac..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub +++ /dev/null @@ -1,26 +0,0 @@ -* Subcircuit LOGIC_ADDER
-.subckt LOGIC_ADDER a b cin sum carry
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-* u2 a b net-_u2-pad3_ d_and
-* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3 a b net-_u3-pad3_ d_xor
-* u5 net-_u3-pad3_ cin sum d_xor
-* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends LOGIC_ADDER
\ No newline at end of file |