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| author | nilshah98 | 2019-07-02 16:42:20 +0530 |
|---|---|---|
| committer | nilshah98 | 2019-07-02 16:46:12 +0530 |
| commit | b085a3df519debbc99acf4ded7e118a1690d6665 (patch) | |
| tree | 0fc3e5389c2a77a97d1a065875fe87ddee2c23f4 /src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out | |
| parent | e7cd941bc4a48ff8684e4db6b9dff0efeb51fa6e (diff) | |
| download | eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.gz eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.bz2 eSim-b085a3df519debbc99acf4ded7e118a1690d6665.zip | |
Subcircuit added by ECE fellows 2019
Diffstat (limited to 'src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out new file mode 100644 index 00000000..df9bcde6 --- /dev/null +++ b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out @@ -0,0 +1,32 @@ +* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
+
+* u2 a b net-_u2-pad3_ d_and
+* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
+* u3 a b net-_u3-pad3_ d_xor
+* u5 net-_u3-pad3_ cin sum d_xor
+* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
+* u1 a b cin sum carry port
+a1 [a b ] net-_u2-pad3_ u2
+a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
+a3 [a b ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ cin ] sum u5
+a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 10e-03 100e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
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