diff options
| author | saurabhb17 | 2019-07-02 17:08:16 +0530 |
|---|---|---|
| committer | GitHub | 2019-07-02 17:08:16 +0530 |
| commit | 83d93769478a1805083666479d4ff83b875ba955 (patch) | |
| tree | d97a2f3543ab4e5164490495ee19f20352ecb71f /src/SubcircuitLibrary/7485 | |
| parent | 29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (diff) | |
| parent | 8c44f97b533607d057a28e029e42f001270f4fd4 (diff) | |
| download | eSim-83d93769478a1805083666479d4ff83b875ba955.tar.gz eSim-83d93769478a1805083666479d4ff83b875ba955.tar.bz2 eSim-83d93769478a1805083666479d4ff83b875ba955.zip | |
Merge pull request #115 from nilshah98/ese
Adding the work done by FSF 2019 eSim ECE Fellows
Diffstat (limited to 'src/SubcircuitLibrary/7485')
46 files changed, 4686 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/7485/3_and-cache.lib b/src/SubcircuitLibrary/7485/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/3_and.cir b/src/SubcircuitLibrary/7485/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/7485/3_and.cir.out b/src/SubcircuitLibrary/7485/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/3_and.pro b/src/SubcircuitLibrary/7485/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/7485/3_and.sch b/src/SubcircuitLibrary/7485/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/3_and.sub b/src/SubcircuitLibrary/7485/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and-cache.lib b/src/SubcircuitLibrary/7485/4_and-cache.lib new file mode 100644 index 00000000..cb84d8f2 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/4_and-rescue.lib b/src/SubcircuitLibrary/7485/4_and-rescue.lib new file mode 100644 index 00000000..6b2c17f7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/4_and.cir b/src/SubcircuitLibrary/7485/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/7485/4_and.cir.out b/src/SubcircuitLibrary/7485/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/4_and.pro b/src/SubcircuitLibrary/7485/4_and.pro new file mode 100644 index 00000000..814ad76a --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/7485/4_and.sch b/src/SubcircuitLibrary/7485/4_and.sch new file mode 100644 index 00000000..2d8296d4 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/4_and.sub b/src/SubcircuitLibrary/7485/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and-cache.lib b/src/SubcircuitLibrary/7485/5_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/5_and.cir b/src/SubcircuitLibrary/7485/5_and.cir new file mode 100644 index 00000000..ca1199bd --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
+U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
+U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/7485/5_and.cir.out b/src/SubcircuitLibrary/7485/5_and.cir.out new file mode 100644 index 00000000..20d3f8a5 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/5_and.pro b/src/SubcircuitLibrary/7485/5_and.pro new file mode 100644 index 00000000..a9d6304f --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_PSpice
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
+LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/7485/5_and.sch b/src/SubcircuitLibrary/7485/5_and.sch new file mode 100644 index 00000000..0d86cdec --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60 0000 C CNN
+F 1 "3_and" H 4750 3850 60 0000 C CNN
+F 2 "" H 3800 3350 60 0000 C CNN
+F 3 "" H 3800 3350 60 0000 C CNN
+ 1 3800 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60 0000 C CNN
+F 1 "d_and" H 4700 3500 60 0000 C CNN
+F 2 "" H 4650 3400 60 0000 C CNN
+F 3 "" H 4650 3400 60 0000 C CNN
+ 1 4650 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60 0000 C CNN
+F 1 "d_and" H 5600 3300 60 0000 C CNN
+F 2 "" H 5550 3200 60 0000 C CNN
+F 3 "" H 5550 3200 60 0000 C CNN
+ 1 5550 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5100 3100 5100 2950
+Wire Wire Line
+ 5100 3200 5100 3350
+Wire Wire Line
+ 4250 2850 4250 2700
+Wire Wire Line
+ 4250 2700 3600 2700
+Wire Wire Line
+ 4250 2950 4150 2950
+Wire Wire Line
+ 4150 2950 4150 2900
+Wire Wire Line
+ 4150 2900 3600 2900
+Wire Wire Line
+ 4200 3300 3600 3300
+Wire Wire Line
+ 4250 3050 4250 3100
+Wire Wire Line
+ 4250 3100 3600 3100
+Wire Wire Line
+ 4200 3400 4200 3500
+Wire Wire Line
+ 4200 3500 3600 3500
+Wire Wire Line
+ 6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30 0000 C CNN
+F 1 "PORT" H 3350 2700 30 0000 C CNN
+F 2 "" H 3350 2700 60 0000 C CNN
+F 3 "" H 3350 2700 60 0000 C CNN
+ 1 3350 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30 0000 C CNN
+F 1 "PORT" H 3350 2900 30 0000 C CNN
+F 2 "" H 3350 2900 60 0000 C CNN
+F 3 "" H 3350 2900 60 0000 C CNN
+ 2 3350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30 0000 C CNN
+F 1 "PORT" H 3350 3100 30 0000 C CNN
+F 2 "" H 3350 3100 60 0000 C CNN
+F 3 "" H 3350 3100 60 0000 C CNN
+ 3 3350 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30 0000 C CNN
+F 1 "PORT" H 3350 3300 30 0000 C CNN
+F 2 "" H 3350 3300 60 0000 C CNN
+F 3 "" H 3350 3300 60 0000 C CNN
+ 4 3350 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30 0000 C CNN
+F 1 "PORT" H 3350 3500 30 0000 C CNN
+F 2 "" H 3350 3500 60 0000 C CNN
+F 3 "" H 3350 3500 60 0000 C CNN
+ 5 3350 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30 0000 C CNN
+F 1 "PORT" H 6750 3150 30 0000 C CNN
+F 2 "" H 6750 3150 60 0000 C CNN
+F 3 "" H 6750 3150 60 0000 C CNN
+ 6 6750 3150
+ -1 0 0 1
+$EndComp
+Text Notes 3800 2700 0 60 ~ 12
+in1
+Text Notes 3800 2900 0 60 ~ 12
+in2
+Text Notes 3800 3100 0 60 ~ 12
+in3
+Text Notes 3800 3300 0 60 ~ 12
+in4
+Text Notes 3800 3500 0 60 ~ 12
+in5
+Text Notes 6150 3150 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/5_and.sub b/src/SubcircuitLibrary/7485/5_and.sub new file mode 100644 index 00000000..9d929fcb --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_nor-cache.lib b/src/SubcircuitLibrary/7485/5_nor-cache.lib new file mode 100644 index 00000000..7098010f --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/5_nor.cir b/src/SubcircuitLibrary/7485/5_nor.cir new file mode 100644 index 00000000..0e4db1ea --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.cir @@ -0,0 +1,19 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/5_nor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:34:56 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and + +.end diff --git a/src/SubcircuitLibrary/7485/5_nor.cir.out b/src/SubcircuitLibrary/7485/5_nor.cir.out new file mode 100644 index 00000000..bc90e004 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.cir.out @@ -0,0 +1,42 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir + +.include 5_and.sub +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/5_nor.pro b/src/SubcircuitLibrary/7485/5_nor.pro new file mode 100644 index 00000000..4716d4ae --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.pro @@ -0,0 +1,73 @@ +update=Tue Jun 25 23:32:34 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/7485/5_nor.sch b/src/SubcircuitLibrary/7485/5_nor.sch new file mode 100644 index 00000000..6bb6fcb8 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.sch @@ -0,0 +1,275 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 5D126275 +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5D126276 +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5D126277 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5D126278 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5D126279 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5D12627A +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5D12627B +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5D12627C +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D12627D +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D12627E +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D12627F +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D126280 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D126281 +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5D126282 +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +Text Notes 2400 2350 0 60 ~ 12 +in1 +Text Notes 2400 2550 0 60 ~ 12 +in2 +Text Notes 2400 2750 0 60 ~ 12 +in3 +Text Notes 2400 2950 0 60 ~ 12 +in4 +Text Notes 2400 3150 0 60 ~ 12 +in5 +Text Notes 2400 3300 0 60 ~ 12 +in6 +Text Notes 6350 3250 0 60 ~ 12 +out +$Comp +L 5_and X1 +U 1 1 5D1262D5 +P 4600 2850 +F 0 "X1" H 4650 2750 60 0000 C CNN +F 1 "5_and" H 4700 3000 60 0000 C CNN +F 2 "" H 4600 2850 60 0000 C CNN +F 3 "" H 4600 2850 60 0000 C CNN + 1 4600 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/5_nor.sub b/src/SubcircuitLibrary/7485/5_nor.sub new file mode 100644 index 00000000..dbcdb750 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor.sub @@ -0,0 +1,36 @@ +* Subcircuit 5_nor +.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir +.include 5_and.sub +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nor
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml new file mode 100644 index 00000000..75f5258c --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485-cache.lib b/src/SubcircuitLibrary/7485/7485-cache.lib new file mode 100644 index 00000000..eb9a059e --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485-cache.lib @@ -0,0 +1,177 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_nor +# +DEF 5_nor X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_nor" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 400 60 0 0 0 name~is~c_gate Normal 0 C C +T 0 50 450 60 0 0 0 subcircuit~file Normal 0 C C +A 150 0 316 716 -716 0 1 0 N 250 300 250 -300 +P 2 0 1 0 -300 300 250 300 N +P 4 0 1 0 -300 300 -300 -300 200 -300 250 -300 N +X in1 1 -500 250 200 R 50 50 1 1 I I +X in2 2 -500 150 200 R 50 50 1 1 I I +X in3 3 -500 50 200 R 50 50 1 1 I I +X in4 4 -500 -50 200 R 50 50 1 1 I I +X in5 5 -500 -150 200 R 50 50 1 1 I I +X in6 6 -500 -250 200 R 50 50 1 1 I I +X out 7 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/7485.cir b/src/SubcircuitLibrary/7485/7485.cir new file mode 100644 index 00000000..87188910 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.cir @@ -0,0 +1,42 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/7485/7485.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:22:51 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and +U2 Net-_U1-Pad15_ Net-_U1-Pad1_ Net-_U18-Pad2_ d_nand +U7 Net-_U18-Pad2_ Net-_U1-Pad1_ Net-_U14-Pad2_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U19 Net-_U1-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +U18 Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U8 Net-_U1-Pad13_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and +U3 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U3-Pad3_ d_nand +U9 Net-_U3-Pad3_ Net-_U1-Pad14_ Net-_U15-Pad2_ d_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U12 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U5 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U12-Pad2_ d_nand +U13 Net-_U12-Pad2_ Net-_U1-Pad9_ Net-_U13-Pad3_ d_and +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor +U10 Net-_U1-Pad12_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U4 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nand +U11 Net-_U10-Pad2_ Net-_U1-Pad11_ Net-_U11-Pad3_ d_and +U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +X7 Net-_U1-Pad14_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad2_ 3_and +X8 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X12-Pad3_ 4_and +X3 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U1-Pad12_ Net-_X1-Pad4_ 4_and +X2 Net-_U14-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad13_ Net-_X1-Pad5_ 3_and +X6 Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad10_ Net-_X1-Pad3_ 5_and +X5 Net-_U1-Pad4_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad2_ 5_and +X4 Net-_U1-Pad3_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad1_ 5_and +X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X11-Pad6_ 5_and +X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X10-Pad6_ 5_and +X9 Net-_U1-Pad9_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X12-Pad4_ 5_and +X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad6_ 5_and +X12 Net-_U19-Pad3_ Net-_X12-Pad2_ Net-_X12-Pad3_ Net-_X12-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad5_ 5_nor +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad7_ 5_nor + +.end diff --git a/src/SubcircuitLibrary/7485/7485.cir.out b/src/SubcircuitLibrary/7485/7485.cir.out new file mode 100644 index 00000000..76e4fe6d --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.cir.out @@ -0,0 +1,101 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir + +.include 5_nor.sub +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +* u6 net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u18 net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and +x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and +x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and +x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and +x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and +x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and +x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and +x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and +x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor +a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/7485.pro b/src/SubcircuitLibrary/7485/7485.pro new file mode 100644 index 00000000..fee23d1f --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.pro @@ -0,0 +1,43 @@ +update=Tue Jun 25 23:21:38 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName10=eSim_Subckt diff --git a/src/SubcircuitLibrary/7485/7485.sch b/src/SubcircuitLibrary/7485/7485.sch new file mode 100644 index 00000000..32175173 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.sch @@ -0,0 +1,1017 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:7485-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 1300 60 0000 C CNN +F 2 "" H 3150 1200 60 0000 C CNN +F 3 "" H 3150 1200 60 0000 C CNN + 1 3150 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U2 +U 1 1 5C9A246F +P 2100 1450 +F 0 "U2" H 2100 1450 60 0000 C CNN +F 1 "d_nand" H 2150 1550 60 0000 C CNN +F 2 "" H 2100 1450 60 0000 C CNN +F 3 "" H 2100 1450 60 0000 C CNN + 1 2100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C9A24BA +P 3150 1600 +F 0 "U7" H 3150 1600 60 0000 C CNN +F 1 "d_and" H 3200 1700 60 0000 C CNN +F 2 "" H 3150 1600 60 0000 C CNN +F 3 "" H 3150 1600 60 0000 C CNN + 1 3150 1600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 5C9A252F +P 4050 1400 +F 0 "U14" H 4050 1400 60 0000 C CNN +F 1 "d_nor" H 4100 1500 60 0000 C CNN +F 2 "" H 4050 1400 60 0000 C CNN +F 3 "" H 4050 1400 60 0000 C CNN + 1 4050 1400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C9A2580 +P 6900 1000 +F 0 "U19" H 6900 1000 60 0000 C CNN +F 1 "d_and" H 6950 1100 60 0000 C CNN +F 2 "" H 6900 1000 60 0000 C CNN +F 3 "" H 6900 1000 60 0000 C CNN + 1 6900 1000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5C9A32FD +P 6350 6900 +F 0 "U18" H 6350 6900 60 0000 C CNN +F 1 "d_and" H 6400 7000 60 0000 C CNN +F 2 "" H 6350 6900 60 0000 C CNN +F 3 "" H 6350 6900 60 0000 C CNN + 1 6350 6900 + 1 0 0 1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A39D8 +P 3250 2600 +F 0 "U8" H 3250 2600 60 0000 C CNN +F 1 "d_and" H 3300 2700 60 0000 C CNN +F 2 "" H 3250 2600 60 0000 C CNN +F 3 "" H 3250 2600 60 0000 C CNN + 1 3250 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 5C9A39DE +P 2200 2850 +F 0 "U3" H 2200 2850 60 0000 C CNN +F 1 "d_nand" H 2250 2950 60 0000 C CNN +F 2 "" H 2200 2850 60 0000 C CNN +F 3 "" H 2200 2850 60 0000 C CNN + 1 2200 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 5C9A39E4 +P 3250 3000 +F 0 "U9" H 3250 3000 60 0000 C CNN +F 1 "d_and" H 3300 3100 60 0000 C CNN +F 2 "" H 3250 3000 60 0000 C CNN +F 3 "" H 3250 3000 60 0000 C CNN + 1 3250 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 5C9A39EA +P 4150 2800 +F 0 "U15" H 4150 2800 60 0000 C CNN +F 1 "d_nor" H 4200 2900 60 0000 C CNN +F 2 "" H 4150 2800 60 0000 C CNN +F 3 "" H 4150 2800 60 0000 C CNN + 1 4150 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 5C9A3B56 +P 3600 4950 +F 0 "U12" H 3600 4950 60 0000 C CNN +F 1 "d_and" H 3650 5050 60 0000 C CNN +F 2 "" H 3600 4950 60 0000 C CNN +F 3 "" H 3600 4950 60 0000 C CNN + 1 3600 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 5C9A3B5C +P 2550 5200 +F 0 "U5" H 2550 5200 60 0000 C CNN +F 1 "d_nand" H 2600 5300 60 0000 C CNN +F 2 "" H 2550 5200 60 0000 C CNN +F 3 "" H 2550 5200 60 0000 C CNN + 1 2550 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5C9A3B62 +P 3600 5350 +F 0 "U13" H 3600 5350 60 0000 C CNN +F 1 "d_and" H 3650 5450 60 0000 C CNN +F 2 "" H 3600 5350 60 0000 C CNN +F 3 "" H 3600 5350 60 0000 C CNN + 1 3600 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U17 +U 1 1 5C9A3B68 +P 4500 5150 +F 0 "U17" H 4500 5150 60 0000 C CNN +F 1 "d_nor" H 4550 5250 60 0000 C CNN +F 2 "" H 4500 5150 60 0000 C CNN +F 3 "" H 4500 5150 60 0000 C CNN + 1 4500 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 5C9A3C6D +P 3400 3750 +F 0 "U10" H 3400 3750 60 0000 C CNN +F 1 "d_and" H 3450 3850 60 0000 C CNN +F 2 "" H 3400 3750 60 0000 C CNN +F 3 "" H 3400 3750 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 5C9A3C73 +P 2350 4000 +F 0 "U4" H 2350 4000 60 0000 C CNN +F 1 "d_nand" H 2400 4100 60 0000 C CNN +F 2 "" H 2350 4000 60 0000 C CNN +F 3 "" H 2350 4000 60 0000 C CNN + 1 2350 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 5C9A3C79 +P 3400 4150 +F 0 "U11" H 3400 4150 60 0000 C CNN +F 1 "d_and" H 3450 4250 60 0000 C CNN +F 2 "" H 3400 4150 60 0000 C CNN +F 3 "" H 3400 4150 60 0000 C CNN + 1 3400 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U16 +U 1 1 5C9A3C7F +P 4300 3950 +F 0 "U16" H 4300 3950 60 0000 C CNN +F 1 "d_nor" H 4350 4050 60 0000 C CNN +F 2 "" H 4300 3950 60 0000 C CNN +F 3 "" H 4300 3950 60 0000 C CNN + 1 4300 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 1300 3600 1150 +Wire Wire Line + 3600 1400 3600 1550 +Wire Wire Line + 2700 1000 2700 4700 +Wire Wire Line + 2700 1600 1550 1600 +Wire Wire Line + 1550 1600 1550 1450 +Wire Wire Line + 1100 1450 1650 1450 +Wire Wire Line + 1100 1350 1650 1350 +Wire Wire Line + 1550 1350 1550 1100 +Wire Wire Line + 1550 1100 2700 1100 +Wire Wire Line + 2550 1400 2700 1400 +Connection ~ 2700 1400 +Connection ~ 1550 1350 +Connection ~ 1550 1450 +Wire Wire Line + 3700 2700 3700 2550 +Wire Wire Line + 3700 2800 3700 2950 +Wire Wire Line + 2800 2000 2800 4600 +Wire Wire Line + 2800 3000 1650 3000 +Wire Wire Line + 1650 3000 1650 2850 +Wire Wire Line + 1200 2850 1750 2850 +Wire Wire Line + 1200 2750 1750 2750 +Wire Wire Line + 1650 2750 1650 2500 +Wire Wire Line + 1650 2500 2800 2500 +Wire Wire Line + 2650 2800 2800 2800 +Connection ~ 2800 2800 +Connection ~ 1650 2750 +Connection ~ 1650 2850 +Wire Wire Line + 4050 5050 4050 4900 +Wire Wire Line + 4050 5150 4050 5300 +Wire Wire Line + 3150 4950 3150 5850 +Wire Wire Line + 3150 5350 2000 5350 +Wire Wire Line + 2000 5350 2000 5200 +Wire Wire Line + 1250 5200 2100 5200 +Wire Wire Line + 1250 5100 2100 5100 +Wire Wire Line + 2000 5100 2000 4850 +Wire Wire Line + 2000 4850 3150 4850 +Wire Wire Line + 3000 5150 3150 5150 +Connection ~ 3150 5150 +Connection ~ 2000 5100 +Connection ~ 2000 5200 +Wire Wire Line + 3850 3850 3850 3700 +Wire Wire Line + 3850 3950 3850 4100 +Wire Wire Line + 2950 3200 2950 4350 +Wire Wire Line + 2950 4150 1800 4150 +Wire Wire Line + 1800 4150 1800 4000 +Wire Wire Line + 1350 4000 1900 4000 +Wire Wire Line + 1200 3900 1900 3900 +Wire Wire Line + 1800 3900 1800 3650 +Wire Wire Line + 1800 3650 2950 3650 +Wire Wire Line + 2800 3950 2950 3950 +Connection ~ 2950 3950 +Connection ~ 1800 3900 +Connection ~ 1800 4000 +Wire Wire Line + 1400 1350 1400 7000 +Wire Wire Line + 1400 7000 5900 7000 +Connection ~ 1400 1350 +Wire Wire Line + 1250 5200 1250 5300 +Wire Wire Line + 5900 6900 2900 6900 +Wire Wire Line + 2900 6900 2900 4700 +Wire Wire Line + 2900 4700 2700 4700 +Connection ~ 2700 1500 +Wire Wire Line + 5950 6750 1450 6750 +Wire Wire Line + 1450 6750 1450 2750 +Connection ~ 1450 2750 +Wire Wire Line + 5950 6650 2950 6650 +Wire Wire Line + 2950 6650 2950 4600 +Wire Wire Line + 2950 4600 2800 4600 +Connection ~ 2800 2900 +Wire Wire Line + 5100 6550 5950 6550 +Wire Wire Line + 5100 1350 5100 6550 +Wire Wire Line + 4500 1350 6500 1350 +Wire Wire Line + 1500 1450 1500 900 +Wire Wire Line + 1500 900 6450 900 +Connection ~ 1500 1450 +Wire Wire Line + 2700 1000 6450 1000 +Connection ~ 2700 1200 +Wire Wire Line + 6500 1150 4500 1150 +Wire Wire Line + 4500 1150 4500 1900 +Wire Wire Line + 4500 1900 1600 1900 +Wire Wire Line + 1600 1900 1600 2850 +Connection ~ 1600 2850 +Wire Wire Line + 6500 1250 4550 1250 +Wire Wire Line + 4550 1250 4550 2000 +Wire Wire Line + 4550 2000 2800 2000 +Connection ~ 2800 2600 +Connection ~ 5100 1350 +Wire Wire Line + 6500 1500 4600 1500 +Wire Wire Line + 4600 1500 4600 2100 +Wire Wire Line + 4600 2100 1750 2100 +Wire Wire Line + 1750 2100 1750 4000 +Connection ~ 1750 4000 +Wire Wire Line + 6500 1600 4650 1600 +Wire Wire Line + 4650 1600 4650 3200 +Wire Wire Line + 4650 3200 2950 3200 +Connection ~ 2950 3750 +Wire Wire Line + 6500 1700 5100 1700 +Connection ~ 5100 1700 +Wire Wire Line + 6500 1800 5250 1800 +Wire Wire Line + 5250 1800 5250 6100 +Wire Wire Line + 5250 2750 4600 2750 +Wire Wire Line + 6500 1950 1500 1950 +Wire Wire Line + 1500 1950 1500 5200 +Connection ~ 1500 5200 +Wire Wire Line + 6500 2050 4950 2050 +Wire Wire Line + 4950 2050 4950 4300 +Wire Wire Line + 4950 4300 3150 4300 +Wire Wire Line + 3150 4300 3150 5000 +Connection ~ 3150 5000 +Wire Wire Line + 6500 2150 5100 2150 +Connection ~ 5100 2150 +Wire Wire Line + 6500 2250 5250 2250 +Connection ~ 5250 2250 +Wire Wire Line + 6500 2350 5350 2350 +Wire Wire Line + 5350 2350 5350 5550 +Wire Wire Line + 5350 3900 4750 3900 +Wire Wire Line + 6500 2500 5100 2500 +Connection ~ 5100 2500 +Wire Wire Line + 6500 2600 5250 2600 +Connection ~ 5250 2600 +Wire Wire Line + 6500 2700 5350 2700 +Connection ~ 5350 2700 +Wire Wire Line + 6500 2800 5450 2800 +Wire Wire Line + 5450 2800 5450 5100 +Wire Wire Line + 4950 5100 5950 5100 +Wire Wire Line + 6500 2900 5550 2900 +Wire Wire Line + 5550 2900 5550 3250 +Wire Wire Line + 5550 3250 1050 3250 +Wire Wire Line + 6500 3050 5100 3050 +Connection ~ 5100 3050 +Wire Wire Line + 5250 3150 6500 3150 +Connection ~ 5250 2750 +Wire Wire Line + 6500 3250 5700 3250 +Wire Wire Line + 5700 3250 5700 3200 +Wire Wire Line + 5700 3200 5350 3200 +Connection ~ 5350 3200 +Wire Wire Line + 6500 3350 5450 3350 +Connection ~ 5450 3350 +Wire Wire Line + 4800 3450 6500 3450 +Wire Wire Line + 4800 3400 4800 3450 +Wire Wire Line + 1050 3400 4800 3400 +Wire Wire Line + 5950 3450 5950 4450 +Connection ~ 5950 3450 +Wire Wire Line + 5950 4550 5450 4550 +Connection ~ 5450 4550 +Wire Wire Line + 5350 4650 5950 4650 +Connection ~ 5350 3900 +Wire Wire Line + 5250 4750 5950 4750 +Connection ~ 5250 3150 +Wire Wire Line + 5950 4850 5100 4850 +Connection ~ 5100 4850 +Wire Wire Line + 5950 5400 5100 5400 +Connection ~ 5100 5400 +Wire Wire Line + 5950 5750 5100 5750 +Connection ~ 5100 5750 +Wire Wire Line + 5950 5000 4800 5000 +Wire Wire Line + 4800 5000 4800 3550 +Wire Wire Line + 4800 3550 1050 3550 +Connection ~ 5450 5100 +Wire Wire Line + 5350 5200 5950 5200 +Connection ~ 5350 4650 +Wire Wire Line + 5250 5300 5950 5300 +Connection ~ 5250 4750 +Wire Wire Line + 5950 5950 1800 5950 +Wire Wire Line + 1800 5950 1800 5100 +Connection ~ 1800 5100 +Wire Wire Line + 5950 6400 1600 6400 +Wire Wire Line + 1600 6400 1600 3900 +Connection ~ 1600 3900 +Wire Wire Line + 5950 6300 5100 6300 +Connection ~ 5100 6300 +Wire Wire Line + 5350 5550 5950 5550 +Connection ~ 5350 5200 +Wire Wire Line + 5250 5650 5950 5650 +Connection ~ 5250 5300 +Wire Wire Line + 3150 5850 5950 5850 +Connection ~ 3150 5250 +Wire Wire Line + 5250 6100 5950 6100 +Connection ~ 5250 5650 +Wire Wire Line + 5950 6200 3000 6200 +Wire Wire Line + 3000 6200 3000 4350 +Wire Wire Line + 3000 4350 2950 4350 +Connection ~ 2950 4050 +Wire Wire Line + 8400 3950 5950 3950 +Connection ~ 5950 3950 +Wire Wire Line + 8400 3750 5100 3750 +Connection ~ 5100 3750 +Wire Wire Line + 8400 3850 5250 3850 +Connection ~ 5250 3850 +Wire Wire Line + 8400 4050 5350 4050 +Connection ~ 5350 4050 +Wire Wire Line + 8400 4150 5450 4150 +Connection ~ 5450 4150 +Wire Wire Line + 8400 1800 8400 950 +Wire Wire Line + 8400 950 7350 950 +Wire Wire Line + 8400 1900 8200 1900 +Wire Wire Line + 8200 1900 8200 1250 +Wire Wire Line + 8200 1250 7350 1250 +Wire Wire Line + 8400 2000 8050 2000 +Wire Wire Line + 8050 2000 8050 1650 +Wire Wire Line + 8050 1650 7400 1650 +Wire Wire Line + 7500 2150 7800 2150 +Wire Wire Line + 7800 2150 7800 2100 +Wire Wire Line + 7800 2100 8400 2100 +Wire Wire Line + 8400 2200 7900 2200 +Wire Wire Line + 7900 2200 7900 2700 +Wire Wire Line + 7900 2700 7500 2700 +Wire Wire Line + 7500 3250 8050 3250 +Wire Wire Line + 8050 3250 8050 2300 +Wire Wire Line + 8050 2300 8400 2300 +Wire Wire Line + 8200 5200 8200 4650 +Wire Wire Line + 8200 4650 6950 4650 +Wire Wire Line + 8200 5300 8050 5300 +Wire Wire Line + 8050 5300 8050 5200 +Wire Wire Line + 8050 5200 6950 5200 +Wire Wire Line + 8200 5400 7250 5400 +Wire Wire Line + 7250 5400 7250 5750 +Wire Wire Line + 7250 5750 6950 5750 +Wire Wire Line + 6850 6250 6850 5850 +Wire Wire Line + 6850 5850 7350 5850 +Wire Wire Line + 7350 5850 7350 5500 +Wire Wire Line + 7350 5500 8200 5500 +Wire Wire Line + 6800 6950 6950 6950 +Wire Wire Line + 6950 6950 6950 6200 +Wire Wire Line + 6950 6200 7950 6200 +Wire Wire Line + 7950 6200 7950 5700 +Wire Wire Line + 7950 5700 8200 5700 +$Comp +L PORT U1 +U 15 1 5C9A8539 +P 850 1350 +F 0 "U1" H 900 1450 30 0000 C CNN +F 1 "PORT" H 850 1350 30 0000 C CNN +F 2 "" H 850 1350 60 0000 C CNN +F 3 "" H 850 1350 60 0000 C CNN + 15 850 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A8668 +P 850 1550 +F 0 "U1" H 900 1650 30 0000 C CNN +F 1 "PORT" H 850 1550 30 0000 C CNN +F 2 "" H 850 1550 60 0000 C CNN +F 3 "" H 850 1550 60 0000 C CNN + 1 850 1550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 1550 1100 1450 +$Comp +L PORT U1 +U 13 1 5C9A8815 +P 950 2650 +F 0 "U1" H 1000 2750 30 0000 C CNN +F 1 "PORT" H 950 2650 30 0000 C CNN +F 2 "" H 950 2650 60 0000 C CNN +F 3 "" H 950 2650 60 0000 C CNN + 13 950 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 2650 1200 2750 +$Comp +L PORT U1 +U 14 1 5C9A8B82 +P 950 2850 +F 0 "U1" H 1000 2950 30 0000 C CNN +F 1 "PORT" H 950 2850 30 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 14 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C9A8C46 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 12 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C9A8D2C +P 950 4100 +F 0 "U1" H 1000 4200 30 0000 C CNN +F 1 "PORT" H 950 4100 30 0000 C CNN +F 2 "" H 950 4100 60 0000 C CNN +F 3 "" H 950 4100 60 0000 C CNN + 11 950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9A8DBD +P 1000 5100 +F 0 "U1" H 1050 5200 30 0000 C CNN +F 1 "PORT" H 1000 5100 30 0000 C CNN +F 2 "" H 1000 5100 60 0000 C CNN +F 3 "" H 1000 5100 60 0000 C CNN + 10 1000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9A8E65 +P 1000 5300 +F 0 "U1" H 1050 5400 30 0000 C CNN +F 1 "PORT" H 1000 5300 30 0000 C CNN +F 2 "" H 1000 5300 60 0000 C CNN +F 3 "" H 1000 5300 60 0000 C CNN + 9 1000 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A8EEE +P 800 3150 +F 0 "U1" H 850 3250 30 0000 C CNN +F 1 "PORT" H 800 3150 30 0000 C CNN +F 2 "" H 800 3150 60 0000 C CNN +F 3 "" H 800 3150 60 0000 C CNN + 2 800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A8F9C +P 800 3400 +F 0 "U1" H 850 3500 30 0000 C CNN +F 1 "PORT" H 800 3400 30 0000 C CNN +F 2 "" H 800 3400 60 0000 C CNN +F 3 "" H 800 3400 60 0000 C CNN + 3 800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A9031 +P 800 3600 +F 0 "U1" H 850 3700 30 0000 C CNN +F 1 "PORT" H 800 3600 30 0000 C CNN +F 2 "" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 4 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 5 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 5 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 6 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 7 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$Comp +L 3_and X7 +U 1 1 5D1262A3 +P 6850 1300 +F 0 "X7" H 6950 1250 60 0000 C CNN +F 1 "3_and" H 7000 1450 60 0000 C CNN +F 2 "" H 6850 1300 60 0000 C CNN +F 3 "" H 6850 1300 60 0000 C CNN + 1 6850 1300 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 5D126302 +P 6900 1650 +F 0 "X8" H 6950 1600 60 0000 C CNN +F 1 "4_and" H 7000 1750 60 0000 C CNN +F 2 "" H 6900 1650 60 0000 C CNN +F 3 "" H 6900 1650 60 0000 C CNN + 1 6900 1650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5D12638A +P 6350 6250 +F 0 "X3" H 6400 6200 60 0000 C CNN +F 1 "4_and" H 6450 6350 60 0000 C CNN +F 2 "" H 6350 6250 60 0000 C CNN +F 3 "" H 6350 6250 60 0000 C CNN + 1 6350 6250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 5D126462 +P 6300 6700 +F 0 "X2" H 6400 6650 60 0000 C CNN +F 1 "3_and" H 6450 6850 60 0000 C CNN +F 2 "" H 6300 6700 60 0000 C CNN +F 3 "" H 6300 6700 60 0000 C CNN + 1 6300 6700 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 5D126552 +P 6400 5750 +F 0 "X6" H 6450 5650 60 0000 C CNN +F 1 "5_and" H 6500 5900 60 0000 C CNN +F 2 "" H 6400 5750 60 0000 C CNN +F 3 "" H 6400 5750 60 0000 C CNN + 1 6400 5750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 5D1265DF +P 6400 5200 +F 0 "X5" H 6450 5100 60 0000 C CNN +F 1 "5_and" H 6500 5350 60 0000 C CNN +F 2 "" H 6400 5200 60 0000 C CNN +F 3 "" H 6400 5200 60 0000 C CNN + 1 6400 5200 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 5D12666C +P 6400 4650 +F 0 "X4" H 6450 4550 60 0000 C CNN +F 1 "5_and" H 6500 4800 60 0000 C CNN +F 2 "" H 6400 4650 60 0000 C CNN +F 3 "" H 6400 4650 60 0000 C CNN + 1 6400 4650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 5D126706 +P 6950 3250 +F 0 "X11" H 7000 3150 60 0000 C CNN +F 1 "5_and" H 7050 3400 60 0000 C CNN +F 2 "" H 6950 3250 60 0000 C CNN +F 3 "" H 6950 3250 60 0000 C CNN + 1 6950 3250 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 5D1267CB +P 6950 2700 +F 0 "X10" H 7000 2600 60 0000 C CNN +F 1 "5_and" H 7050 2850 60 0000 C CNN +F 2 "" H 6950 2700 60 0000 C CNN +F 3 "" H 6950 2700 60 0000 C CNN + 1 6950 2700 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 5D12686F +P 6950 2150 +F 0 "X9" H 7000 2050 60 0000 C CNN +F 1 "5_and" H 7050 2300 60 0000 C CNN +F 2 "" H 6950 2150 60 0000 C CNN +F 3 "" H 6950 2150 60 0000 C CNN + 1 6950 2150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X13 +U 1 1 5D126AC3 +P 8850 3950 +F 0 "X13" H 8900 3850 60 0000 C CNN +F 1 "5_and" H 8950 4100 60 0000 C CNN +F 2 "" H 8850 3950 60 0000 C CNN +F 3 "" H 8850 3950 60 0000 C CNN + 1 8850 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5D127AEB +P 10550 650 +F 0 "U1" H 10600 750 30 0000 C CNN +F 1 "PORT" H 10550 650 30 0000 C CNN +F 2 "" H 10550 650 60 0000 C CNN +F 3 "" H 10550 650 60 0000 C CNN + 8 10550 650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 5D127BBA +P 10550 900 +F 0 "U1" H 10600 1000 30 0000 C CNN +F 1 "PORT" H 10550 900 30 0000 C CNN +F 2 "" H 10550 900 60 0000 C CNN +F 3 "" H 10550 900 60 0000 C CNN + 16 10550 900 + -1 0 0 1 +$EndComp +NoConn ~ 10300 650 +NoConn ~ 10300 900 +NoConn ~ 2950 10200 +$Comp +L 5_nor X12 +U 1 1 5D12919D +P 8900 2050 +F 0 "X12" H 8950 1950 60 0000 C CNN +F 1 "5_nor" H 9000 2200 60 0000 C CNN +F 2 "" H 8900 2050 60 0000 C CNN +F 3 "" H 8900 2050 60 0000 C CNN + 1 8900 2050 + 1 0 0 -1 +$EndComp +$Comp +L 5_nor X1 +U 1 1 5D12935A +P 8700 5450 +F 0 "X1" H 8750 5350 60 0000 C CNN +F 1 "5_nor" H 8800 5600 60 0000 C CNN +F 2 "" H 8700 5450 60 0000 C CNN +F 3 "" H 8700 5450 60 0000 C CNN + 1 8700 5450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/7485.sub b/src/SubcircuitLibrary/7485/7485.sub new file mode 100644 index 00000000..63ea7f3b --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.sub @@ -0,0 +1,95 @@ +* Subcircuit 7485 +.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir +.include 5_nor.sub +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +* u6 net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u18 net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and +x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and +x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and +x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and +x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and +x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and +x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and +x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and +x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor +a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 7485
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml new file mode 100644 index 00000000..124a0047 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor</field></x1><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x9><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor</field></x12><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x13><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485mod-cache.lib b/src/SubcircuitLibrary/7485/7485mod-cache.lib new file mode 100644 index 00000000..f1f7990e --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485mod-cache.lib @@ -0,0 +1,175 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 1500 1050 60 H V C CNN
+F1 "4_and" 1550 1200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
+P 2 0 1 0 1250 1300 1600 1300 N
+P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N
+X in1 1 1050 1250 200 R 50 50 1 1 I
+X in2 2 1050 1150 200 R 50 50 1 1 I
+X in3 3 1050 1050 200 R 50 50 1 1 I
+X in4 4 1050 950 200 R 50 50 1 1 I
+X out 5 1950 1100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 1350 800 60 H V C CNN
+F1 "5_and" 1400 1050 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
+P 2 0 1 0 1050 1150 1450 1150 N
+P 3 0 1 0 1050 1150 1050 650 1450 650 N
+X in1 1 850 1100 200 R 50 50 1 1 I
+X in2 2 850 1000 200 R 50 50 1 1 I
+X in3 3 850 900 200 R 50 50 1 1 I
+X in4 4 850 800 200 R 50 50 1 1 I
+X in5 5 850 700 200 R 50 50 1 1 I
+X out 6 1850 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# c_gate
+#
+DEF c_gate X 0 40 Y Y 1 F N
+F0 "X" 5900 4450 60 H V C CNN
+F1 "c_gate" 5950 4700 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250
+P 2 0 1 0 5550 4850 6100 4850 N
+P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N
+X in1 1 5350 4800 200 R 50 50 1 1 I I
+X in2 2 5350 4700 200 R 50 50 1 1 I I
+X in3 3 5350 4600 200 R 50 50 1 1 I I
+X in4 4 5350 4500 200 R 50 50 1 1 I I
+X in5 5 5350 4400 200 R 50 50 1 1 I I
+X in6 6 5350 4300 200 R 50 50 1 1 I I
+X out 7 6500 4550 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/7485mod.sch b/src/SubcircuitLibrary/7485/7485mod.sch new file mode 100644 index 00000000..9114b802 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485mod.sch @@ -0,0 +1,1007 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:7485-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U6
+U 1 1 5C9A2432
+P 3150 1200
+F 0 "U6" H 3150 1200 60 0000 C CNN
+F 1 "d_and" H 3200 1300 60 0000 C CNN
+F 2 "" H 3150 1200 60 0000 C CNN
+F 3 "" H 3150 1200 60 0000 C CNN
+ 1 3150 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U2
+U 1 1 5C9A246F
+P 2100 1450
+F 0 "U2" H 2100 1450 60 0000 C CNN
+F 1 "d_nand" H 2150 1550 60 0000 C CNN
+F 2 "" H 2100 1450 60 0000 C CNN
+F 3 "" H 2100 1450 60 0000 C CNN
+ 1 2100 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 5C9A24BA
+P 3150 1600
+F 0 "U7" H 3150 1600 60 0000 C CNN
+F 1 "d_and" H 3200 1700 60 0000 C CNN
+F 2 "" H 3150 1600 60 0000 C CNN
+F 3 "" H 3150 1600 60 0000 C CNN
+ 1 3150 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U14
+U 1 1 5C9A252F
+P 4050 1400
+F 0 "U14" H 4050 1400 60 0000 C CNN
+F 1 "d_nor" H 4100 1500 60 0000 C CNN
+F 2 "" H 4050 1400 60 0000 C CNN
+F 3 "" H 4050 1400 60 0000 C CNN
+ 1 4050 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 5C9A2580
+P 6900 1000
+F 0 "U19" H 6900 1000 60 0000 C CNN
+F 1 "d_and" H 6950 1100 60 0000 C CNN
+F 2 "" H 6900 1000 60 0000 C CNN
+F 3 "" H 6900 1000 60 0000 C CNN
+ 1 6900 1000
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X12
+U 1 1 5C9A2DC4
+P 6050 1650
+F 0 "X12" H 6950 1950 60 0000 C CNN
+F 1 "3_and" H 7000 2150 60 0000 C CNN
+F 2 "" H 6050 1650 60 0000 C CNN
+F 3 "" H 6050 1650 60 0000 C CNN
+ 1 6050 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X7
+U 1 1 5C9A2EB7
+P 5450 2750
+F 0 "X7" H 6950 3800 60 0000 C CNN
+F 1 "4_and" H 7000 3950 60 0000 C CNN
+F 2 "" H 5450 2750 60 0000 C CNN
+F 3 "" H 5450 2750 60 0000 C CNN
+ 1 5450 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L 5_and X9
+U 1 1 5C9A2F2E
+P 5650 3050
+F 0 "X9" H 7000 3850 60 0000 C CNN
+F 1 "5_and" H 7050 4100 60 0000 C CNN
+F 2 "" H 5650 3050 60 0000 C CNN
+F 3 "" H 5650 3050 60 0000 C CNN
+ 1 5650 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 5_and X10
+U 1 1 5C9A2F95
+P 5650 3600
+F 0 "X10" H 7000 4400 60 0000 C CNN
+F 1 "5_and" H 7050 4650 60 0000 C CNN
+F 2 "" H 5650 3600 60 0000 C CNN
+F 3 "" H 5650 3600 60 0000 C CNN
+ 1 5650 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L 5_and X11
+U 1 1 5C9A3164
+P 5650 4150
+F 0 "X11" H 7000 4950 60 0000 C CNN
+F 1 "5_and" H 7050 5200 60 0000 C CNN
+F 2 "" H 5650 4150 60 0000 C CNN
+F 3 "" H 5650 4150 60 0000 C CNN
+ 1 5650 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L 5_and X13
+U 1 1 5C9A31B3
+P 7550 4850
+F 0 "X13" H 8900 5650 60 0000 C CNN
+F 1 "5_and" H 8950 5900 60 0000 C CNN
+F 2 "" H 7550 4850 60 0000 C CNN
+F 3 "" H 7550 4850 60 0000 C CNN
+ 1 7550 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 5C9A32FD
+P 6350 6900
+F 0 "U18" H 6350 6900 60 0000 C CNN
+F 1 "d_and" H 6400 7000 60 0000 C CNN
+F 2 "" H 6350 6900 60 0000 C CNN
+F 3 "" H 6350 6900 60 0000 C CNN
+ 1 6350 6900
+ 1 0 0 1
+$EndComp
+$Comp
+L 3_and X8
+U 1 1 5C9A3303
+P 5500 6250
+F 0 "X8" H 6400 6550 60 0000 C CNN
+F 1 "3_and" H 6450 6750 60 0000 C CNN
+F 2 "" H 5500 6250 60 0000 C CNN
+F 3 "" H 5500 6250 60 0000 C CNN
+ 1 5500 6250
+ 1 0 0 1
+$EndComp
+$Comp
+L 4_and X3
+U 1 1 5C9A3309
+P 4900 5150
+F 0 "X3" H 6400 6200 60 0000 C CNN
+F 1 "4_and" H 6450 6350 60 0000 C CNN
+F 2 "" H 4900 5150 60 0000 C CNN
+F 3 "" H 4900 5150 60 0000 C CNN
+ 1 4900 5150
+ 1 0 0 1
+$EndComp
+$Comp
+L 5_and X6
+U 1 1 5C9A330F
+P 5100 4850
+F 0 "X6" H 6450 5650 60 0000 C CNN
+F 1 "5_and" H 6500 5900 60 0000 C CNN
+F 2 "" H 5100 4850 60 0000 C CNN
+F 3 "" H 5100 4850 60 0000 C CNN
+ 1 5100 4850
+ 1 0 0 1
+$EndComp
+$Comp
+L 5_and X5
+U 1 1 5C9A3315
+P 5100 4300
+F 0 "X5" H 6450 5100 60 0000 C CNN
+F 1 "5_and" H 6500 5350 60 0000 C CNN
+F 2 "" H 5100 4300 60 0000 C CNN
+F 3 "" H 5100 4300 60 0000 C CNN
+ 1 5100 4300
+ 1 0 0 1
+$EndComp
+$Comp
+L 5_and X4
+U 1 1 5C9A331B
+P 5100 3750
+F 0 "X4" H 6450 4550 60 0000 C CNN
+F 1 "5_and" H 6500 4800 60 0000 C CNN
+F 2 "" H 5100 3750 60 0000 C CNN
+F 3 "" H 5100 3750 60 0000 C CNN
+ 1 5100 3750
+ 1 0 0 1
+$EndComp
+$Comp
+L d_and U8
+U 1 1 5C9A39D8
+P 3250 2600
+F 0 "U8" H 3250 2600 60 0000 C CNN
+F 1 "d_and" H 3300 2700 60 0000 C CNN
+F 2 "" H 3250 2600 60 0000 C CNN
+F 3 "" H 3250 2600 60 0000 C CNN
+ 1 3250 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U3
+U 1 1 5C9A39DE
+P 2200 2850
+F 0 "U3" H 2200 2850 60 0000 C CNN
+F 1 "d_nand" H 2250 2950 60 0000 C CNN
+F 2 "" H 2200 2850 60 0000 C CNN
+F 3 "" H 2200 2850 60 0000 C CNN
+ 1 2200 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U9
+U 1 1 5C9A39E4
+P 3250 3000
+F 0 "U9" H 3250 3000 60 0000 C CNN
+F 1 "d_and" H 3300 3100 60 0000 C CNN
+F 2 "" H 3250 3000 60 0000 C CNN
+F 3 "" H 3250 3000 60 0000 C CNN
+ 1 3250 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 5C9A39EA
+P 4150 2800
+F 0 "U15" H 4150 2800 60 0000 C CNN
+F 1 "d_nor" H 4200 2900 60 0000 C CNN
+F 2 "" H 4150 2800 60 0000 C CNN
+F 3 "" H 4150 2800 60 0000 C CNN
+ 1 4150 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 5C9A3B56
+P 3600 4950
+F 0 "U12" H 3600 4950 60 0000 C CNN
+F 1 "d_and" H 3650 5050 60 0000 C CNN
+F 2 "" H 3600 4950 60 0000 C CNN
+F 3 "" H 3600 4950 60 0000 C CNN
+ 1 3600 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U5
+U 1 1 5C9A3B5C
+P 2550 5200
+F 0 "U5" H 2550 5200 60 0000 C CNN
+F 1 "d_nand" H 2600 5300 60 0000 C CNN
+F 2 "" H 2550 5200 60 0000 C CNN
+F 3 "" H 2550 5200 60 0000 C CNN
+ 1 2550 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 5C9A3B62
+P 3600 5350
+F 0 "U13" H 3600 5350 60 0000 C CNN
+F 1 "d_and" H 3650 5450 60 0000 C CNN
+F 2 "" H 3600 5350 60 0000 C CNN
+F 3 "" H 3600 5350 60 0000 C CNN
+ 1 3600 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U17
+U 1 1 5C9A3B68
+P 4500 5150
+F 0 "U17" H 4500 5150 60 0000 C CNN
+F 1 "d_nor" H 4550 5250 60 0000 C CNN
+F 2 "" H 4500 5150 60 0000 C CNN
+F 3 "" H 4500 5150 60 0000 C CNN
+ 1 4500 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U10
+U 1 1 5C9A3C6D
+P 3400 3750
+F 0 "U10" H 3400 3750 60 0000 C CNN
+F 1 "d_and" H 3450 3850 60 0000 C CNN
+F 2 "" H 3400 3750 60 0000 C CNN
+F 3 "" H 3400 3750 60 0000 C CNN
+ 1 3400 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 5C9A3C73
+P 2350 4000
+F 0 "U4" H 2350 4000 60 0000 C CNN
+F 1 "d_nand" H 2400 4100 60 0000 C CNN
+F 2 "" H 2350 4000 60 0000 C CNN
+F 3 "" H 2350 4000 60 0000 C CNN
+ 1 2350 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U11
+U 1 1 5C9A3C79
+P 3400 4150
+F 0 "U11" H 3400 4150 60 0000 C CNN
+F 1 "d_and" H 3450 4250 60 0000 C CNN
+F 2 "" H 3400 4150 60 0000 C CNN
+F 3 "" H 3400 4150 60 0000 C CNN
+ 1 3400 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U16
+U 1 1 5C9A3C7F
+P 4300 3950
+F 0 "U16" H 4300 3950 60 0000 C CNN
+F 1 "d_nor" H 4350 4050 60 0000 C CNN
+F 2 "" H 4300 3950 60 0000 C CNN
+F 3 "" H 4300 3950 60 0000 C CNN
+ 1 4300 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L c_gate X2
+U 1 1 5C9A4498
+P 3050 6600
+F 0 "X2" H 3100 6650 60 0000 C CNN
+F 1 "c_gate" H 9000 11300 60 0000 C CNN
+F 2 "" H 3050 6600 60 0000 C CNN
+F 3 "" H 3050 6600 60 0000 C CNN
+ 1 3050 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L c_gate X1
+U 1 1 5C9A465F
+P 2850 10000
+F 0 "X1" H 2900 10050 60 0000 C CNN
+F 1 "c_gate" H 8800 14700 60 0000 C CNN
+F 2 "" H 2850 10000 60 0000 C CNN
+F 3 "" H 2850 10000 60 0000 C CNN
+ 1 2850 10000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3600 1300 3600 1150
+Wire Wire Line
+ 3600 1400 3600 1550
+Wire Wire Line
+ 2700 1000 2700 4700
+Wire Wire Line
+ 2700 1600 1550 1600
+Wire Wire Line
+ 1550 1600 1550 1450
+Wire Wire Line
+ 1100 1450 1650 1450
+Wire Wire Line
+ 1100 1350 1650 1350
+Wire Wire Line
+ 1550 1350 1550 1100
+Wire Wire Line
+ 1550 1100 2700 1100
+Wire Wire Line
+ 2550 1400 2700 1400
+Connection ~ 2700 1400
+Connection ~ 1550 1350
+Connection ~ 1550 1450
+Wire Wire Line
+ 3700 2700 3700 2550
+Wire Wire Line
+ 3700 2800 3700 2950
+Wire Wire Line
+ 2800 2000 2800 4600
+Wire Wire Line
+ 2800 3000 1650 3000
+Wire Wire Line
+ 1650 3000 1650 2850
+Wire Wire Line
+ 1200 2850 1750 2850
+Wire Wire Line
+ 1200 2750 1750 2750
+Wire Wire Line
+ 1650 2750 1650 2500
+Wire Wire Line
+ 1650 2500 2800 2500
+Wire Wire Line
+ 2650 2800 2800 2800
+Connection ~ 2800 2800
+Connection ~ 1650 2750
+Connection ~ 1650 2850
+Wire Wire Line
+ 4050 5050 4050 4900
+Wire Wire Line
+ 4050 5150 4050 5300
+Wire Wire Line
+ 3150 4950 3150 5850
+Wire Wire Line
+ 3150 5350 2000 5350
+Wire Wire Line
+ 2000 5350 2000 5200
+Wire Wire Line
+ 1250 5200 2100 5200
+Wire Wire Line
+ 1250 5100 2100 5100
+Wire Wire Line
+ 2000 5100 2000 4850
+Wire Wire Line
+ 2000 4850 3150 4850
+Wire Wire Line
+ 3000 5150 3150 5150
+Connection ~ 3150 5150
+Connection ~ 2000 5100
+Connection ~ 2000 5200
+Wire Wire Line
+ 3850 3850 3850 3700
+Wire Wire Line
+ 3850 3950 3850 4100
+Wire Wire Line
+ 2950 3200 2950 4350
+Wire Wire Line
+ 2950 4150 1800 4150
+Wire Wire Line
+ 1800 4150 1800 4000
+Wire Wire Line
+ 1350 4000 1900 4000
+Wire Wire Line
+ 1200 3900 1900 3900
+Wire Wire Line
+ 1800 3900 1800 3650
+Wire Wire Line
+ 1800 3650 2950 3650
+Wire Wire Line
+ 2800 3950 2950 3950
+Connection ~ 2950 3950
+Connection ~ 1800 3900
+Connection ~ 1800 4000
+Wire Wire Line
+ 1400 1350 1400 7000
+Wire Wire Line
+ 1400 7000 5900 7000
+Connection ~ 1400 1350
+Wire Wire Line
+ 1250 5200 1250 5300
+Wire Wire Line
+ 5900 6900 2900 6900
+Wire Wire Line
+ 2900 6900 2900 4700
+Wire Wire Line
+ 2900 4700 2700 4700
+Connection ~ 2700 1500
+Wire Wire Line
+ 5950 6750 1450 6750
+Wire Wire Line
+ 1450 6750 1450 2750
+Connection ~ 1450 2750
+Wire Wire Line
+ 5950 6650 2950 6650
+Wire Wire Line
+ 2950 6650 2950 4600
+Wire Wire Line
+ 2950 4600 2800 4600
+Connection ~ 2800 2900
+Wire Wire Line
+ 5100 6550 5950 6550
+Wire Wire Line
+ 5100 1350 5100 6550
+Wire Wire Line
+ 4500 1350 6500 1350
+Wire Wire Line
+ 1500 1450 1500 900
+Wire Wire Line
+ 1500 900 6450 900
+Connection ~ 1500 1450
+Wire Wire Line
+ 2700 1000 6450 1000
+Connection ~ 2700 1200
+Wire Wire Line
+ 6500 1150 4500 1150
+Wire Wire Line
+ 4500 1150 4500 1900
+Wire Wire Line
+ 4500 1900 1600 1900
+Wire Wire Line
+ 1600 1900 1600 2850
+Connection ~ 1600 2850
+Wire Wire Line
+ 6500 1250 4550 1250
+Wire Wire Line
+ 4550 1250 4550 2000
+Wire Wire Line
+ 4550 2000 2800 2000
+Connection ~ 2800 2600
+Connection ~ 5100 1350
+Wire Wire Line
+ 6500 1500 4600 1500
+Wire Wire Line
+ 4600 1500 4600 2100
+Wire Wire Line
+ 4600 2100 1750 2100
+Wire Wire Line
+ 1750 2100 1750 4000
+Connection ~ 1750 4000
+Wire Wire Line
+ 6500 1600 4650 1600
+Wire Wire Line
+ 4650 1600 4650 3200
+Wire Wire Line
+ 4650 3200 2950 3200
+Connection ~ 2950 3750
+Wire Wire Line
+ 6500 1700 5100 1700
+Connection ~ 5100 1700
+Wire Wire Line
+ 6500 1800 5250 1800
+Wire Wire Line
+ 5250 1800 5250 6100
+Wire Wire Line
+ 5250 2750 4600 2750
+Wire Wire Line
+ 6500 1950 1500 1950
+Wire Wire Line
+ 1500 1950 1500 5200
+Connection ~ 1500 5200
+Wire Wire Line
+ 6500 2050 4950 2050
+Wire Wire Line
+ 4950 2050 4950 4300
+Wire Wire Line
+ 4950 4300 3150 4300
+Wire Wire Line
+ 3150 4300 3150 5000
+Connection ~ 3150 5000
+Wire Wire Line
+ 6500 2150 5100 2150
+Connection ~ 5100 2150
+Wire Wire Line
+ 6500 2250 5250 2250
+Connection ~ 5250 2250
+Wire Wire Line
+ 6500 2350 5350 2350
+Wire Wire Line
+ 5350 2350 5350 5550
+Wire Wire Line
+ 5350 3900 4750 3900
+Wire Wire Line
+ 6500 2500 5100 2500
+Connection ~ 5100 2500
+Wire Wire Line
+ 6500 2600 5250 2600
+Connection ~ 5250 2600
+Wire Wire Line
+ 6500 2700 5350 2700
+Connection ~ 5350 2700
+Wire Wire Line
+ 6500 2800 5450 2800
+Wire Wire Line
+ 5450 2800 5450 5100
+Wire Wire Line
+ 4950 5100 5950 5100
+Wire Wire Line
+ 6500 2900 5550 2900
+Wire Wire Line
+ 5550 2900 5550 3250
+Wire Wire Line
+ 5550 3250 1050 3250
+Wire Wire Line
+ 6500 3050 5100 3050
+Connection ~ 5100 3050
+Wire Wire Line
+ 5250 3150 6500 3150
+Connection ~ 5250 2750
+Wire Wire Line
+ 6500 3250 5700 3250
+Wire Wire Line
+ 5700 3250 5700 3200
+Wire Wire Line
+ 5700 3200 5350 3200
+Connection ~ 5350 3200
+Wire Wire Line
+ 6500 3350 5450 3350
+Connection ~ 5450 3350
+Wire Wire Line
+ 4800 3450 6500 3450
+Wire Wire Line
+ 4800 3450 4800 3400
+Wire Wire Line
+ 4800 3400 1050 3400
+Wire Wire Line
+ 5950 3450 5950 4450
+Connection ~ 5950 3450
+Wire Wire Line
+ 5950 4550 5450 4550
+Connection ~ 5450 4550
+Wire Wire Line
+ 5350 4650 5950 4650
+Connection ~ 5350 3900
+Wire Wire Line
+ 5250 4750 5950 4750
+Connection ~ 5250 3150
+Wire Wire Line
+ 5950 4850 5100 4850
+Connection ~ 5100 4850
+Wire Wire Line
+ 5950 5400 5100 5400
+Connection ~ 5100 5400
+Wire Wire Line
+ 5950 5750 5100 5750
+Connection ~ 5100 5750
+Wire Wire Line
+ 5950 5000 4800 5000
+Wire Wire Line
+ 4800 5000 4800 3550
+Wire Wire Line
+ 4800 3550 1050 3550
+Connection ~ 5450 5100
+Wire Wire Line
+ 5350 5200 5950 5200
+Connection ~ 5350 4650
+Wire Wire Line
+ 5250 5300 5950 5300
+Connection ~ 5250 4750
+Wire Wire Line
+ 5950 5950 1800 5950
+Wire Wire Line
+ 1800 5950 1800 5100
+Connection ~ 1800 5100
+Wire Wire Line
+ 5950 6400 1600 6400
+Wire Wire Line
+ 1600 6400 1600 3900
+Connection ~ 1600 3900
+Wire Wire Line
+ 5950 6300 5100 6300
+Connection ~ 5100 6300
+Wire Wire Line
+ 5350 5550 5950 5550
+Connection ~ 5350 5200
+Wire Wire Line
+ 5250 5650 5950 5650
+Connection ~ 5250 5300
+Wire Wire Line
+ 3150 5850 5950 5850
+Connection ~ 3150 5250
+Wire Wire Line
+ 5250 6100 5950 6100
+Connection ~ 5250 5650
+Wire Wire Line
+ 5950 6200 3000 6200
+Wire Wire Line
+ 3000 6200 3000 4350
+Wire Wire Line
+ 3000 4350 2950 4350
+Connection ~ 2950 4050
+Wire Wire Line
+ 8400 3950 5950 3950
+Connection ~ 5950 3950
+Wire Wire Line
+ 8400 3750 5100 3750
+Connection ~ 5100 3750
+Wire Wire Line
+ 8400 3850 5250 3850
+Connection ~ 5250 3850
+Wire Wire Line
+ 8400 4050 5350 4050
+Connection ~ 5350 4050
+Wire Wire Line
+ 8400 4150 5450 4150
+Connection ~ 5450 4150
+Wire Wire Line
+ 8400 1800 8400 950
+Wire Wire Line
+ 8400 950 7350 950
+Wire Wire Line
+ 8400 1900 8200 1900
+Wire Wire Line
+ 8200 1900 8200 1250
+Wire Wire Line
+ 8200 1250 7350 1250
+Wire Wire Line
+ 8400 2000 8050 2000
+Wire Wire Line
+ 8050 2000 8050 1650
+Wire Wire Line
+ 8050 1650 7400 1650
+Wire Wire Line
+ 7500 2150 7800 2150
+Wire Wire Line
+ 7800 2150 7800 2100
+Wire Wire Line
+ 7800 2100 8400 2100
+Wire Wire Line
+ 8400 2200 7900 2200
+Wire Wire Line
+ 7900 2200 7900 2700
+Wire Wire Line
+ 7900 2700 7500 2700
+Wire Wire Line
+ 7500 3250 8050 3250
+Wire Wire Line
+ 8050 3250 8050 2300
+Wire Wire Line
+ 8050 2300 8400 2300
+Wire Wire Line
+ 8200 5200 8200 4650
+Wire Wire Line
+ 8200 4650 6950 4650
+Wire Wire Line
+ 8200 5300 8050 5300
+Wire Wire Line
+ 8050 5300 8050 5200
+Wire Wire Line
+ 8050 5200 6950 5200
+Wire Wire Line
+ 8200 5400 7250 5400
+Wire Wire Line
+ 7250 5400 7250 5750
+Wire Wire Line
+ 7250 5750 6950 5750
+Wire Wire Line
+ 6850 6250 6850 5850
+Wire Wire Line
+ 6850 5850 7350 5850
+Wire Wire Line
+ 7350 5850 7350 5500
+Wire Wire Line
+ 7350 5500 8200 5500
+Wire Wire Line
+ 6800 6950 6950 6950
+Wire Wire Line
+ 6950 6950 6950 6200
+Wire Wire Line
+ 6950 6200 7950 6200
+Wire Wire Line
+ 7950 6200 7950 5700
+Wire Wire Line
+ 7950 5700 8200 5700
+$Comp
+L PORT U1
+U 4 1 5C9A8539
+P 850 1350
+F 0 "U1" H 900 1450 30 0000 C CNN
+F 1 "PORT" H 850 1350 30 0000 C CNN
+F 2 "" H 850 1350 60 0000 C CNN
+F 3 "" H 850 1350 60 0000 C CNN
+ 4 850 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A8668
+P 850 1550
+F 0 "U1" H 900 1650 30 0000 C CNN
+F 1 "PORT" H 850 1550 30 0000 C CNN
+F 2 "" H 850 1550 60 0000 C CNN
+F 3 "" H 850 1550 60 0000 C CNN
+ 5 850 1550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1100 1550 1100 1450
+$Comp
+L PORT U1
+U 6 1 5C9A8815
+P 950 2650
+F 0 "U1" H 1000 2750 30 0000 C CNN
+F 1 "PORT" H 950 2650 30 0000 C CNN
+F 2 "" H 950 2650 60 0000 C CNN
+F 3 "" H 950 2650 60 0000 C CNN
+ 6 950 2650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1200 2650 1200 2750
+$Comp
+L PORT U1
+U 7 1 5C9A8B82
+P 950 2850
+F 0 "U1" H 1000 2950 30 0000 C CNN
+F 1 "PORT" H 950 2850 30 0000 C CNN
+F 2 "" H 950 2850 60 0000 C CNN
+F 3 "" H 950 2850 60 0000 C CNN
+ 7 950 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5C9A8C46
+P 950 3900
+F 0 "U1" H 1000 4000 30 0000 C CNN
+F 1 "PORT" H 950 3900 30 0000 C CNN
+F 2 "" H 950 3900 60 0000 C CNN
+F 3 "" H 950 3900 60 0000 C CNN
+ 8 950 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5C9A8D2C
+P 950 4100
+F 0 "U1" H 1000 4200 30 0000 C CNN
+F 1 "PORT" H 950 4100 30 0000 C CNN
+F 2 "" H 950 4100 60 0000 C CNN
+F 3 "" H 950 4100 60 0000 C CNN
+ 9 950 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5C9A8DBD
+P 1000 5100
+F 0 "U1" H 1050 5200 30 0000 C CNN
+F 1 "PORT" H 1000 5100 30 0000 C CNN
+F 2 "" H 1000 5100 60 0000 C CNN
+F 3 "" H 1000 5100 60 0000 C CNN
+ 10 1000 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5C9A8E65
+P 1000 5300
+F 0 "U1" H 1050 5400 30 0000 C CNN
+F 1 "PORT" H 1000 5300 30 0000 C CNN
+F 2 "" H 1000 5300 60 0000 C CNN
+F 3 "" H 1000 5300 60 0000 C CNN
+ 11 1000 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A8EEE
+P 800 3150
+F 0 "U1" H 850 3250 30 0000 C CNN
+F 1 "PORT" H 800 3150 30 0000 C CNN
+F 2 "" H 800 3150 60 0000 C CNN
+F 3 "" H 800 3150 60 0000 C CNN
+ 1 800 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A8F9C
+P 800 3400
+F 0 "U1" H 850 3500 30 0000 C CNN
+F 1 "PORT" H 800 3400 30 0000 C CNN
+F 2 "" H 800 3400 60 0000 C CNN
+F 3 "" H 800 3400 60 0000 C CNN
+ 2 800 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A9031
+P 800 3600
+F 0 "U1" H 850 3700 30 0000 C CNN
+F 1 "PORT" H 800 3600 30 0000 C CNN
+F 2 "" H 800 3600 60 0000 C CNN
+F 3 "" H 800 3600 60 0000 C CNN
+ 3 800 3600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1050 3250 1050 3150
+Wire Wire Line
+ 1050 3550 1050 3600
+Wire Wire Line
+ 1350 4000 1350 4100
+Wire Wire Line
+ 1350 4100 1200 4100
+Wire Wire Line
+ 9550 2050 9850 2050
+Wire Wire Line
+ 9400 3950 9850 3950
+Wire Wire Line
+ 9350 5450 9900 5450
+$Comp
+L PORT U1
+U 12 1 5C9A9B26
+P 10100 2050
+F 0 "U1" H 10150 2150 30 0000 C CNN
+F 1 "PORT" H 10100 2050 30 0000 C CNN
+F 2 "" H 10100 2050 60 0000 C CNN
+F 3 "" H 10100 2050 60 0000 C CNN
+ 12 10100 2050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5C9A9BCA
+P 10100 3950
+F 0 "U1" H 10150 4050 30 0000 C CNN
+F 1 "PORT" H 10100 3950 30 0000 C CNN
+F 2 "" H 10100 3950 60 0000 C CNN
+F 3 "" H 10100 3950 60 0000 C CNN
+ 13 10100 3950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5C9A9CA0
+P 10150 5450
+F 0 "U1" H 10200 5550 30 0000 C CNN
+F 1 "PORT" H 10150 5450 30 0000 C CNN
+F 2 "" H 10150 5450 60 0000 C CNN
+F 3 "" H 10150 5450 60 0000 C CNN
+ 14 10150 5450
+ -1 0 0 1
+$EndComp
+Text Notes 9650 2000 0 60 ~ 12
+A>B
+Text Notes 9600 3900 0 60 ~ 12
+A=B\n
+Text Notes 9600 5400 0 60 ~ 12
+A<B\n
+Text Notes 1250 5100 0 60 ~ 12
+A0
+Text Notes 1200 5400 0 60 ~ 12
+B0
+Text Notes 1300 3900 2 60 ~ 12
+A1
+Text Notes 1300 4200 2 60 ~ 12
+B1
+Text Notes 1250 3250 2 60 ~ 12
+A<B
+Text Notes 1250 3400 2 60 ~ 12
+A=B
+Text Notes 1250 3550 2 60 ~ 12
+A>B
+Text Notes 1350 2750 2 60 ~ 12
+A2
+Text Notes 1350 2950 2 60 ~ 12
+B2
+Text Notes 1300 1350 2 60 ~ 12
+A3
+Text Notes 1300 1550 2 60 ~ 12
+B3
+Wire Wire Line
+ 8200 5600 7450 5600
+Wire Wire Line
+ 7450 5600 7450 6050
+Wire Wire Line
+ 7450 6050 6900 6050
+Wire Wire Line
+ 6800 6650 6800 6300
+Wire Wire Line
+ 6800 6300 6900 6300
+Wire Wire Line
+ 6900 6300 6900 6050
+Wire Notes Line
+ 500 3000 1350 3000
+Wire Notes Line
+ 1350 3000 1350 3750
+Wire Notes Line
+ 1350 3750 500 3750
+Wire Notes Line
+ 500 3750 500 3000
+Text Notes 600 3000 3 60 ~ 12
+Cascading Inputs
+Wire Notes Line
+ 9500 1550 9500 6050
+Wire Notes Line
+ 9500 6050 10550 6050
+Wire Notes Line
+ 10550 6050 10550 1550
+Wire Notes Line
+ 10550 1550 9500 1550
+Text Notes 9900 3400 0 60 ~ 12
+Outputs
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/analysis b/src/SubcircuitLibrary/7485/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/7485/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate-cache.lib b/src/SubcircuitLibrary/7485/c_gate-cache.lib new file mode 100644 index 00000000..e83bf18b --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 1350 800 60 H V C CNN
+F1 "5_and" 1400 1050 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
+P 2 0 1 0 1050 1150 1450 1150 N
+P 3 0 1 0 1050 1150 1050 650 1450 650 N
+X in1 1 850 1100 200 R 50 50 1 1 I
+X in2 2 850 1000 200 R 50 50 1 1 I
+X in3 3 850 900 200 R 50 50 1 1 I
+X in4 4 850 800 200 R 50 50 1 1 I
+X in5 5 850 700 200 R 50 50 1 1 I
+X out 6 1850 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/c_gate.cir b/src/SubcircuitLibrary/7485/c_gate.cir new file mode 100644 index 00000000..865e4229 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and
+U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter
+U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter
+U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter
+U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter
+U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out new file mode 100644 index 00000000..249e9b8f --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.cir.out @@ -0,0 +1,42 @@ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
+
+.include 5_and.sub
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
+* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter
+* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter
+* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 net-_u1-pad4_ net-_u5-pad2_ u5
+a6 net-_u1-pad5_ net-_u6-pad2_ u6
+a7 net-_u1-pad6_ net-_u7-pad2_ u7
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/c_gate.pro b/src/SubcircuitLibrary/7485/c_gate.pro new file mode 100644 index 00000000..0ac5f7d7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.pro @@ -0,0 +1,57 @@ +update=03/26/19 19:06:59
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=texas
+LibName2=intel
+LibName3=audio
+LibName4=interface
+LibName5=digital-audio
+LibName6=philips
+LibName7=display
+LibName8=cypress
+LibName9=siliconi
+LibName10=opto
+LibName11=atmel
+LibName12=contrib
+LibName13=valves
+LibName14=eSim_Analog
+LibName15=eSim_Devices
+LibName16=eSim_Digital
+LibName17=eSim_Hybrid
+LibName18=eSim_Miscellaneous
+LibName19=eSim_Plot
+LibName20=eSim_Power
+LibName21=eSim_PSpice
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/7485/c_gate.sch b/src/SubcircuitLibrary/7485/c_gate.sch new file mode 100644 index 00000000..8205ff7f --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.sch @@ -0,0 +1,246 @@ +EESchema Schematic File Version 2
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:c_gate-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 5_and X1
+U 1 1 5C9A2B0B
+P 3300 3750
+F 0 "X1" H 4650 4550 60 0000 C CNN
+F 1 "5_and" H 4700 4800 60 0000 C CNN
+F 2 "" H 3300 3750 60 0000 C CNN
+F 3 "" H 3300 3750 60 0000 C CNN
+ 1 3300 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U8
+U 1 1 5C9A2B3E
+P 5600 3300
+F 0 "U8" H 5600 3300 60 0000 C CNN
+F 1 "d_and" H 5650 3400 60 0000 C CNN
+F 2 "" H 5600 3300 60 0000 C CNN
+F 3 "" H 5600 3300 60 0000 C CNN
+ 1 5600 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5150 3200 5150 2850
+Wire Wire Line
+ 4150 2650 4150 2350
+Wire Wire Line
+ 4150 2350 3600 2350
+Wire Wire Line
+ 4150 2750 4050 2750
+Wire Wire Line
+ 4050 2750 4050 2550
+Wire Wire Line
+ 4050 2550 3600 2550
+Wire Wire Line
+ 4150 2850 3700 2850
+Wire Wire Line
+ 3700 2850 3700 2750
+Wire Wire Line
+ 3700 2750 3600 2750
+Wire Wire Line
+ 4150 2950 3600 2950
+Wire Wire Line
+ 4150 3050 4150 3150
+Wire Wire Line
+ 4150 3150 3600 3150
+Wire Wire Line
+ 5150 3300 3600 3300
+$Comp
+L d_inverter U2
+U 1 1 5C9A2CDC
+P 3300 2350
+F 0 "U2" H 3300 2250 60 0000 C CNN
+F 1 "d_inverter" H 3300 2500 60 0000 C CNN
+F 2 "" H 3350 2300 60 0000 C CNN
+F 3 "" H 3350 2300 60 0000 C CNN
+ 1 3300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 5C9A2D06
+P 3300 2550
+F 0 "U3" H 3300 2450 60 0000 C CNN
+F 1 "d_inverter" H 3300 2700 60 0000 C CNN
+F 2 "" H 3350 2500 60 0000 C CNN
+F 3 "" H 3350 2500 60 0000 C CNN
+ 1 3300 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 5C9A2D26
+P 3300 2750
+F 0 "U4" H 3300 2650 60 0000 C CNN
+F 1 "d_inverter" H 3300 2900 60 0000 C CNN
+F 2 "" H 3350 2700 60 0000 C CNN
+F 3 "" H 3350 2700 60 0000 C CNN
+ 1 3300 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 5C9A2D49
+P 3300 2950
+F 0 "U5" H 3300 2850 60 0000 C CNN
+F 1 "d_inverter" H 3300 3100 60 0000 C CNN
+F 2 "" H 3350 2900 60 0000 C CNN
+F 3 "" H 3350 2900 60 0000 C CNN
+ 1 3300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 5C9A2D73
+P 3300 3150
+F 0 "U6" H 3300 3050 60 0000 C CNN
+F 1 "d_inverter" H 3300 3300 60 0000 C CNN
+F 2 "" H 3350 3100 60 0000 C CNN
+F 3 "" H 3350 3100 60 0000 C CNN
+ 1 3300 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 5C9A2D9E
+P 3300 3300
+F 0 "U7" H 3300 3200 60 0000 C CNN
+F 1 "d_inverter" H 3300 3450 60 0000 C CNN
+F 2 "" H 3350 3250 60 0000 C CNN
+F 3 "" H 3350 3250 60 0000 C CNN
+ 1 3300 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3000 2350 2000 2350
+Wire Wire Line
+ 3000 2550 2000 2550
+Wire Wire Line
+ 3000 2750 2050 2750
+Wire Wire Line
+ 3000 2950 2050 2950
+Wire Wire Line
+ 3000 3150 2050 3150
+Wire Wire Line
+ 3000 3300 2050 3300
+Wire Wire Line
+ 6050 3250 6950 3250
+$Comp
+L PORT U1
+U 1 1 5C9A2F6F
+P 1750 2350
+F 0 "U1" H 1800 2450 30 0000 C CNN
+F 1 "PORT" H 1750 2350 30 0000 C CNN
+F 2 "" H 1750 2350 60 0000 C CNN
+F 3 "" H 1750 2350 60 0000 C CNN
+ 1 1750 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A2FAB
+P 1750 2550
+F 0 "U1" H 1800 2650 30 0000 C CNN
+F 1 "PORT" H 1750 2550 30 0000 C CNN
+F 2 "" H 1750 2550 60 0000 C CNN
+F 3 "" H 1750 2550 60 0000 C CNN
+ 2 1750 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2FDD
+P 1800 2750
+F 0 "U1" H 1850 2850 30 0000 C CNN
+F 1 "PORT" H 1800 2750 30 0000 C CNN
+F 2 "" H 1800 2750 60 0000 C CNN
+F 3 "" H 1800 2750 60 0000 C CNN
+ 3 1800 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A301A
+P 1800 2950
+F 0 "U1" H 1850 3050 30 0000 C CNN
+F 1 "PORT" H 1800 2950 30 0000 C CNN
+F 2 "" H 1800 2950 60 0000 C CNN
+F 3 "" H 1800 2950 60 0000 C CNN
+ 4 1800 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A3052
+P 1800 3150
+F 0 "U1" H 1850 3250 30 0000 C CNN
+F 1 "PORT" H 1800 3150 30 0000 C CNN
+F 2 "" H 1800 3150 60 0000 C CNN
+F 3 "" H 1800 3150 60 0000 C CNN
+ 5 1800 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A308D
+P 1800 3300
+F 0 "U1" H 1850 3400 30 0000 C CNN
+F 1 "PORT" H 1800 3300 30 0000 C CNN
+F 2 "" H 1800 3300 60 0000 C CNN
+F 3 "" H 1800 3300 60 0000 C CNN
+ 6 1800 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5C9A30DD
+P 7200 3250
+F 0 "U1" H 7250 3350 30 0000 C CNN
+F 1 "PORT" H 7200 3250 30 0000 C CNN
+F 2 "" H 7200 3250 60 0000 C CNN
+F 3 "" H 7200 3250 60 0000 C CNN
+ 7 7200 3250
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/c_gate.sub b/src/SubcircuitLibrary/7485/c_gate.sub new file mode 100644 index 00000000..e7138794 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.sub @@ -0,0 +1,36 @@ +* Subcircuit c_gate
+.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
+.include 5_and.sub
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
+* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter
+* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter
+* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter
+a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 net-_u1-pad4_ net-_u5-pad2_ u5
+a6 net-_u1-pad5_ net-_u6-pad2_ u6
+a7 net-_u1-pad6_ net-_u7-pad2_ u7
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends c_gate
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml new file mode 100644 index 00000000..e51d62de --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |