common code for Win and Linux, merged py2 changes

1 files changed, 42 insertions, 42 deletions

diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out
index 249e9b8f..db7bb2f8 100644
--- a/src/SubcircuitLibrary/7485/c_gate.cir.out
+++ b/src/SubcircuitLibrary/7485/c_gate.cir.out
@@ -1,42 +1,42 @@
-* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir

-

-.include 5_and.sub

-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and

-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and

-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter

-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter

-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter

-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter

-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter

-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter

-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port

-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8

-a2 net-_u1-pad1_ net-_u2-pad2_ u2

-a3 net-_u1-pad2_ net-_u3-pad2_ u3

-a4 net-_u1-pad3_ net-_u4-pad2_ u4

-a5 net-_u1-pad4_ net-_u5-pad2_ u5

-a6 net-_u1-pad5_ net-_u6-pad2_ u6

-a7 net-_u1-pad6_ net-_u7-pad2_ u7

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_inverter, NgSpice Name: d_inverter

-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_inverter, NgSpice Name: d_inverter

-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_inverter, NgSpice Name: d_inverter

-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_inverter, NgSpice Name: d_inverter

-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_inverter, NgSpice Name: d_inverter

-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_inverter, NgSpice Name: d_inverter

-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-.tran 0e-00 0e-00 0e-00

-

-* Control Statements 

-.control

-run

-print allv > plot_data_v.txt

-print alli > plot_data_i.txt

-.endc

-.end

+* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
+
+.include 5_and.sub
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
+* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
+* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
+* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 net-_u1-pad4_ net-_u5-pad2_ u5
+a6 net-_u1-pad5_ net-_u6-pad2_ u6
+a7 net-_u1-pad6_ net-_u7-pad2_ u7
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end