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| author | nilshah98 | 2019-07-02 16:42:20 +0530 |
|---|---|---|
| committer | nilshah98 | 2019-07-02 16:46:12 +0530 |
| commit | b085a3df519debbc99acf4ded7e118a1690d6665 (patch) | |
| tree | 0fc3e5389c2a77a97d1a065875fe87ddee2c23f4 /src/SubcircuitLibrary/74157/74157.cir.out | |
| parent | e7cd941bc4a48ff8684e4db6b9dff0efeb51fa6e (diff) | |
| download | eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.gz eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.bz2 eSim-b085a3df519debbc99acf4ded7e118a1690d6665.zip | |
Subcircuit added by ECE fellows 2019
Diffstat (limited to 'src/SubcircuitLibrary/74157/74157.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/74157/74157.cir.out | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out new file mode 100644 index 00000000..b9a19223 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.cir.out @@ -0,0 +1,45 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir + +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or +* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and +x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and +x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and +x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and +x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23 +a5 net-_u1-pad1_ net-_u3-pad2_ u3 +a6 net-_u1-pad15_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |