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| author | nilshah98 | 2019-07-02 16:42:20 +0530 |
|---|---|---|
| committer | nilshah98 | 2019-07-02 16:46:12 +0530 |
| commit | b085a3df519debbc99acf4ded7e118a1690d6665 (patch) | |
| tree | 0fc3e5389c2a77a97d1a065875fe87ddee2c23f4 /src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub | |
| parent | e7cd941bc4a48ff8684e4db6b9dff0efeb51fa6e (diff) | |
| download | eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.gz eSim-b085a3df519debbc99acf4ded7e118a1690d6665.tar.bz2 eSim-b085a3df519debbc99acf4ded7e118a1690d6665.zip | |
Subcircuit added by ECE fellows 2019
Diffstat (limited to 'src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub')
| -rw-r--r-- | src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub new file mode 100644 index 00000000..0ea4496d --- /dev/null +++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub @@ -0,0 +1,26 @@ +* Subcircuit Full-Adder
+.subckt Full-Adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
+* u5 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
+* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
+* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
+a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
+a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends Full-Adder
\ No newline at end of file |