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authornilshah982019-07-02 16:42:20 +0530
committernilshah982019-07-02 16:46:12 +0530
commitb085a3df519debbc99acf4ded7e118a1690d6665 (patch)
tree0fc3e5389c2a77a97d1a065875fe87ddee2c23f4 /src/SubcircuitLibrary/5_nor/3_and.sub
parente7cd941bc4a48ff8684e4db6b9dff0efeb51fa6e (diff)
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Subcircuit added by ECE fellows 2019
Diffstat (limited to 'src/SubcircuitLibrary/5_nor/3_and.sub')
-rw-r--r--src/SubcircuitLibrary/5_nor/3_and.sub14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/5_nor/3_and.sub b/src/SubcircuitLibrary/5_nor/3_and.sub
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+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file