Subcircuit added by ECE fellows 2019

22 files changed, 1017 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/5_nand/3_and-cache.lib b/src/SubcircuitLibrary/5_nand/3_and-cache.lib
new file mode 100644
index 00000000..0a3ccf7f
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3

+#encoding utf-8

+#

+# PORT

+#

+DEF PORT U 0 40 Y Y 26 F N

+F0 "U" 50 100 30 H V C CNN

+F1 "PORT" 0 0 30 H V C CNN

+F2 "" 0 0 60 H V C CNN

+F3 "" 0 0 60 H V C CNN

+DRAW

+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0

+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50

+S -100 50 100 -50 0 1 0 N

+X ~ 1 250 0 100 L 30 30 1 1 B

+X ~ 2 250 0 100 L 30 30 2 1 B

+X ~ 3 250 0 100 L 30 30 3 1 B

+X ~ 4 250 0 100 L 30 30 4 1 B

+X ~ 5 250 0 100 L 30 30 5 1 B

+X ~ 6 250 0 100 L 30 30 6 1 B

+X ~ 7 250 0 100 L 30 30 7 1 B

+X ~ 8 250 0 100 L 30 30 8 1 B

+X ~ 9 250 0 100 L 30 30 9 1 B

+X ~ 10 250 0 100 L 30 30 10 1 B

+X ~ 11 250 0 100 L 30 30 11 1 B

+X ~ 12 250 0 100 L 30 30 12 1 B

+X ~ 13 250 0 100 L 30 30 13 1 B

+X ~ 14 250 0 100 L 30 30 14 1 B

+X ~ 15 250 0 100 L 30 30 15 1 B

+X ~ 16 250 0 100 L 30 30 16 1 B

+X ~ 17 250 0 100 L 30 30 17 1 B

+X ~ 18 250 0 100 L 30 30 18 1 B

+X ~ 19 250 0 100 L 30 30 19 1 B

+X ~ 20 250 0 100 L 30 30 20 1 B

+X ~ 21 250 0 100 L 30 30 21 1 B

+X ~ 22 250 0 100 L 30 30 22 1 B

+X ~ 23 250 0 100 L 30 30 23 1 B

+X ~ 24 250 0 100 L 30 30 24 1 B

+X ~ 25 250 0 100 L 30 30 25 1 B

+X ~ 26 250 0 100 L 30 30 26 1 B

+ENDDRAW

+ENDDEF

+#

+# d_and

+#

+DEF d_and U 0 40 Y Y 1 F N

+F0 "U" 0 0 60 H V C CNN

+F1 "d_and" 50 100 60 H V C CNN

+F2 "" 0 0 60 H V C CNN

+F3 "" 0 0 60 H V C CNN

+DRAW

+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50

+A 150 49 100 6 900 0 1 0 N 250 50 150 150

+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N

+X IN1 1 -450 100 200 R 50 50 1 1 I

+X IN2 2 -450 0 200 R 50 50 1 1 I

+X OUT 3 450 50 200 L 50 50 1 1 O

+ENDDRAW

+ENDDEF

+#

+#End Library

diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir b/src/SubcircuitLibrary/5_nand/3_and.cir
new file mode 100644
index 00000000..15f8954d
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir

+

+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57

+

+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N

+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

+

+* Sheet Name: /

+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		

+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		

+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		

+

+.end

diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir.out b/src/SubcircuitLibrary/5_nand/3_and.cir.out
new file mode 100644
index 00000000..e3c96645
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir

+

+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and

+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and

+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port

+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2

+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

+.tran 0e-00 0e-00 0e-00

+

+* Control Statements 

+.control

+run

+print allv > plot_data_v.txt

+print alli > plot_data_i.txt

+.endc

+.end

diff --git a/src/SubcircuitLibrary/5_nand/3_and.pro b/src/SubcircuitLibrary/5_nand/3_and.pro
new file mode 100644
index 00000000..0fdf4d25
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/3_and.pro
@@ -0,0 +1,44 @@
+update=05/31/19 15:26:09

+version=1

+last_client=eeschema

+[general]

+version=1

+RootSch=

+BoardNm=

+[pcbnew]

+version=1

+LastNetListRead=

+UseCmpFile=1

+PadDrill=0.600000000000

+PadDrillOvalY=0.600000000000

+PadSizeH=1.500000000000

+PadSizeV=1.500000000000

+PcbTextSizeV=1.500000000000

+PcbTextSizeH=1.500000000000

+PcbTextThickness=0.300000000000

+ModuleTextSizeV=1.000000000000

+ModuleTextSizeH=1.000000000000

+ModuleTextSizeThickness=0.150000000000

+SolderMaskClearance=0.000000000000

+SolderMaskMinWidth=0.000000000000

+DrawSegmentWidth=0.200000000000

+BoardOutlineThickness=0.100000000000

+ModuleOutlineThickness=0.150000000000

+[cvpcb]

+version=1

+NetIExt=net

+[eeschema]

+version=1

+LibDir=../../../kicadSchematicLibrary

+[eeschema/libraries]

+LibName1=eSim_Analog

+LibName2=eSim_Devices

+LibName3=eSim_Digital

+LibName4=eSim_Hybrid

+LibName5=eSim_Miscellaneous

+LibName6=eSim_Plot

+LibName7=eSim_Power

+LibName8=eSim_PSpice

+LibName9=eSim_Sources

+LibName10=eSim_Subckt

+LibName11=eSim_User

diff --git a/src/SubcircuitLibrary/5_nand/3_and.sch b/src/SubcircuitLibrary/5_nand/3_and.sch
new file mode 100644
index 00000000..c853bf49
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2

+LIBS:power

+LIBS:texas

+LIBS:intel

+LIBS:audio

+LIBS:interface

+LIBS:digital-audio

+LIBS:philips

+LIBS:display

+LIBS:cypress

+LIBS:siliconi

+LIBS:opto

+LIBS:atmel

+LIBS:contrib

+LIBS:valves

+LIBS:eSim_Analog

+LIBS:eSim_Devices

+LIBS:eSim_Digital

+LIBS:eSim_Hybrid

+LIBS:eSim_Miscellaneous

+LIBS:eSim_Plot

+LIBS:eSim_Power

+LIBS:eSim_PSpice

+LIBS:eSim_Sources

+LIBS:eSim_Subckt

+LIBS:eSim_User

+LIBS:3_and-cache

+EELAYER 25 0

+EELAYER END

+$Descr A4 11693 8268

+encoding utf-8

+Sheet 1 1

+Title ""

+Date ""

+Rev ""

+Comp ""

+Comment1 ""

+Comment2 ""

+Comment3 ""

+Comment4 ""

+$EndDescr

+$Comp

+L d_and U2

+U 1 1 5C9A24D8

+P 4250 2700

+F 0 "U2" H 4250 2700 60  0000 C CNN

+F 1 "d_and" H 4300 2800 60  0000 C CNN

+F 2 "" H 4250 2700 60  0000 C CNN

+F 3 "" H 4250 2700 60  0000 C CNN

+	1    4250 2700

+	1    0    0    -1  

+$EndComp

+$Comp

+L d_and U3

+U 1 1 5C9A2538

+P 5150 2900

+F 0 "U3" H 5150 2900 60  0000 C CNN

+F 1 "d_and" H 5200 3000 60  0000 C CNN

+F 2 "" H 5150 2900 60  0000 C CNN

+F 3 "" H 5150 2900 60  0000 C CNN

+	1    5150 2900

+	1    0    0    -1  

+$EndComp

+$Comp

+L PORT U1

+U 1 1 5C9A259A

+P 3050 2600

+F 0 "U1" H 3100 2700 30  0000 C CNN

+F 1 "PORT" H 3050 2600 30  0000 C CNN

+F 2 "" H 3050 2600 60  0000 C CNN

+F 3 "" H 3050 2600 60  0000 C CNN

+	1    3050 2600

+	1    0    0    -1  

+$EndComp

+$Comp

+L PORT U1

+U 2 1 5C9A25D9

+P 3050 2800

+F 0 "U1" H 3100 2900 30  0000 C CNN

+F 1 "PORT" H 3050 2800 30  0000 C CNN

+F 2 "" H 3050 2800 60  0000 C CNN

+F 3 "" H 3050 2800 60  0000 C CNN

+	2    3050 2800

+	1    0    0    -1  

+$EndComp

+$Comp

+L PORT U1

+U 3 1 5C9A260A

+P 3050 3100

+F 0 "U1" H 3100 3200 30  0000 C CNN

+F 1 "PORT" H 3050 3100 30  0000 C CNN

+F 2 "" H 3050 3100 60  0000 C CNN

+F 3 "" H 3050 3100 60  0000 C CNN

+	3    3050 3100

+	1    0    0    -1  

+$EndComp

+$Comp

+L PORT U1

+U 4 1 5C9A2637

+P 6900 2850

+F 0 "U1" H 6950 2950 30  0000 C CNN

+F 1 "PORT" H 6900 2850 30  0000 C CNN

+F 2 "" H 6900 2850 60  0000 C CNN

+F 3 "" H 6900 2850 60  0000 C CNN

+	4    6900 2850

+	-1   0    0    1   

+$EndComp

+Wire Wire Line

+	4700 2650 4700 2800

+Wire Wire Line

+	5600 2850 6650 2850

+Wire Wire Line

+	3800 2600 3300 2600

+Wire Wire Line

+	3800 2700 3300 2700

+Wire Wire Line

+	3300 2700 3300 2800

+Wire Wire Line

+	3300 3100 4700 3100

+Wire Wire Line

+	4700 3100 4700 2900

+Text Notes 3500 2600 0    60   ~ 12

+in1

+Text Notes 3450 2800 0    60   ~ 12

+in2\n

+Text Notes 3500 3100 0    60   ~ 12

+in3

+Text Notes 6100 2850 0    60   ~ 12

+out

+$EndSCHEMATC

diff --git a/src/SubcircuitLibrary/5_nand/3_and.sub b/src/SubcircuitLibrary/5_nand/3_and.sub
new file mode 100644
index 00000000..b949ae4f
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and

+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 

+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir

+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and

+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and

+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2

+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

+* Control Statements

+

+.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_and-cache.lib b/src/SubcircuitLibrary/5_nand/5_and-cache.lib
new file mode 100644
index 00000000..4cf915be
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3

+#encoding utf-8

+#

+# 3_and

+#

+DEF 3_and X 0 40 Y Y 1 F N

+F0 "X" 900 300 60 H V C CNN

+F1 "3_and" 950 500 60 H V C CNN

+F2 "" 0 0 60 H V C CNN

+F3 "" 0 0 60 H V C CNN

+DRAW

+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250

+P 2 0 1 0  650 550  1000 550 N

+P 3 0 1 0  650 550  650 250  1000 250 N

+X in1 1 450 500 200 R 50 50 1 1 I

+X in2 2 450 400 200 R 50 50 1 1 I

+X in3 3 450 300 200 R 50 50 1 1 I

+X out 4 1300 400 200 L 50 50 1 1 O

+ENDDRAW

+ENDDEF

+#

+# PORT

+#

+DEF PORT U 0 40 Y Y 26 F N

+F0 "U" 50 100 30 H V C CNN

+F1 "PORT" 0 0 30 H V C CNN

+F2 "" 0 0 60 H V C CNN

+F3 "" 0 0 60 H V C CNN

+DRAW

+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0

+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50

+S -100 50 100 -50 0 1 0 N

+X ~ 1 250 0 100 L 30 30 1 1 B

+X ~ 2 250 0 100 L 30 30 2 1 B

+X ~ 3 250 0 100 L 30 30 3 1 B

+X ~ 4 250 0 100 L 30 30 4 1 B

+X ~ 5 250 0 100 L 30 30 5 1 B

+X ~ 6 250 0 100 L 30 30 6 1 B

+X ~ 7 250 0 100 L 30 30 7 1 B

+X ~ 8 250 0 100 L 30 30 8 1 B

+X ~ 9 250 0 100 L 30 30 9 1 B

+X ~ 10 250 0 100 L 30 30 10 1 B

+X ~ 11 250 0 100 L 30 30 11 1 B

+X ~ 12 250 0 100 L 30 30 12 1 B

+X ~ 13 250 0 100 L 30 30 13 1 B

+X ~ 14 250 0 100 L 30 30 14 1 B

+X ~ 15 250 0 100 L 30 30 15 1 B

+X ~ 16 250 0 100 L 30 30 16 1 B

+X ~ 17 250 0 100 L 30 30 17 1 B

+X ~ 18 250 0 100 L 30 30 18 1 B

+X ~ 19 250 0 100 L 30 30 19 1 B

+X ~ 20 250 0 100 L 30 30 20 1 B

+X ~ 21 250 0 100 L 30 30 21 1 B

+X ~ 22 250 0 100 L 30 30 22 1 B

+X ~ 23 250 0 100 L 30 30 23 1 B

+X ~ 24 250 0 100 L 30 30 24 1 B

+X ~ 25 250 0 100 L 30 30 25 1 B

+X ~ 26 250 0 100 L 30 30 26 1 B

+ENDDRAW

+ENDDEF

+#

+# d_and

+#

+DEF d_and U 0 40 Y Y 1 F N

+F0 "U" 0 0 60 H V C CNN

+F1 "d_and" 50 100 60 H V C CNN

+F2 "" 0 0 60 H V C CNN

+F3 "" 0 0 60 H V C CNN

+DRAW

+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50

+A 150 49 100 6 900 0 1 0 N 250 50 150 150

+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N

+X IN1 1 -450 100 200 R 50 50 1 1 I

+X IN2 2 -450 0 200 R 50 50 1 1 I

+X OUT 3 450 50 200 L 50 50 1 1 O

+ENDDRAW

+ENDDEF

+#

+#End Library

diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir b/src/SubcircuitLibrary/5_nand/5_and.cir
new file mode 100644
index 00000000..ca1199bd
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir

+

+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13

+

+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N

+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

+

+* Sheet Name: /

+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		

+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		

+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		

+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		

+

+.end

diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir.out b/src/SubcircuitLibrary/5_nand/5_and.cir.out
new file mode 100644
index 00000000..20d3f8a5
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir

+

+.include 3_and.sub

+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and

+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and

+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and

+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port

+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2

+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

+.tran 0e-00 0e-00 0e-00

+

+* Control Statements 

+.control

+run

+print allv > plot_data_v.txt

+print alli > plot_data_i.txt

+.endc

+.end

diff --git a/src/SubcircuitLibrary/5_nand/5_and.pro b/src/SubcircuitLibrary/5_nand/5_and.pro
new file mode 100644
index 00000000..a9d6304f
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_and.pro
@@ -0,0 +1,50 @@
+update=06/01/19 11:31:03

+version=1

+last_client=eeschema

+[general]

+version=1

+RootSch=

+BoardNm=

+[pcbnew]

+version=1

+LastNetListRead=

+UseCmpFile=1

+PadDrill=0.600000000000

+PadDrillOvalY=0.600000000000

+PadSizeH=1.500000000000

+PadSizeV=1.500000000000

+PcbTextSizeV=1.500000000000

+PcbTextSizeH=1.500000000000

+PcbTextThickness=0.300000000000

+ModuleTextSizeV=1.000000000000

+ModuleTextSizeH=1.000000000000

+ModuleTextSizeThickness=0.150000000000

+SolderMaskClearance=0.000000000000

+SolderMaskMinWidth=0.000000000000

+DrawSegmentWidth=0.200000000000

+BoardOutlineThickness=0.100000000000

+ModuleOutlineThickness=0.150000000000

+[cvpcb]

+version=1

+NetIExt=net

+[eeschema]

+version=1

+LibDir=../../../kicadSchematicLibrary

+[eeschema/libraries]

+LibName1=cypress

+LibName2=siliconi

+LibName3=opto

+LibName4=atmel

+LibName5=contrib

+LibName6=valves

+LibName7=eSim_Analog

+LibName8=eSim_Devices

+LibName9=eSim_Digital

+LibName10=eSim_Hybrid

+LibName11=eSim_Miscellaneous

+LibName12=eSim_Plot

+LibName13=eSim_Power

+LibName14=eSim_PSpice

+LibName15=eSim_Sources

+LibName16=eSim_Subckt

+LibName17=eSim_User

diff --git a/src/SubcircuitLibrary/5_nand/5_and.sch b/src/SubcircuitLibrary/5_nand/5_and.sch
new file mode 100644
index 00000000..0d86cdec
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2

+LIBS:cypress

+LIBS:siliconi

+LIBS:opto

+LIBS:atmel

+LIBS:contrib

+LIBS:valves

+LIBS:eSim_Analog

+LIBS:eSim_Devices

+LIBS:eSim_Digital

+LIBS:eSim_Hybrid

+LIBS:eSim_Miscellaneous

+LIBS:eSim_Plot

+LIBS:eSim_Power

+LIBS:eSim_PSpice

+LIBS:eSim_Sources

+LIBS:eSim_Subckt

+LIBS:eSim_User

+LIBS:5_and-cache

+EELAYER 25 0

+EELAYER END

+$Descr A4 11693 8268

+encoding utf-8

+Sheet 1 1

+Title ""

+Date ""

+Rev ""

+Comp ""

+Comment1 ""

+Comment2 ""

+Comment3 ""

+Comment4 ""

+$EndDescr

+$Comp

+L 3_and X1

+U 1 1 5C9A2741

+P 3800 3350

+F 0 "X1" H 4700 3650 60  0000 C CNN

+F 1 "3_and" H 4750 3850 60  0000 C CNN

+F 2 "" H 3800 3350 60  0000 C CNN

+F 3 "" H 3800 3350 60  0000 C CNN

+	1    3800 3350

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diff --git a/src/SubcircuitLibrary/5_nand/5_and.sub b/src/SubcircuitLibrary/5_nand/5_and.sub
new file mode 100644
index 00000000..9d929fcb
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and

+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 

+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir

+.include 3_and.sub

+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and

+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and

+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and

+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2

+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

+* Schematic Name: d_and, NgSpice Name: d_and

+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

+* Control Statements

+

+.ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml
new file mode 100644
index 00000000..ae2c08a7
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib b/src/SubcircuitLibrary/5_nand/5_nand-cache.lib
new file mode 100644
index 00000000..cb517be1
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_nand-cache.lib
@@ -0,0 +1,78 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 50 -100 60 H V C CNN
+F1 "5_and" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -250 250 150 250 N
+P 3 0 1 0 -250 250 -250 -250 150 -250 N
+X in1 1 -450 200 200 R 50 50 1 1 I
+X in2 2 -450 100 200 R 50 50 1 1 I
+X in3 3 -450 0 200 R 50 50 1 1 I
+X in4 4 -450 -100 200 R 50 50 1 1 I
+X in5 5 -450 -200 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir b/src/SubcircuitLibrary/5_nand/5_nand.cir
new file mode 100644
index 00000000..e833d0f4
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_nand.cir
@@ -0,0 +1,13 @@
+* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir.out b/src/SubcircuitLibrary/5_nand/5_nand.cir.out
new file mode 100644
index 00000000..164de911
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_nand.cir.out
@@ -0,0 +1,18 @@
+* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
+
+.include 5_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
+* u2  net-_u2-pad1_ net-_u1-pad6_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 net-_u2-pad1_ net-_u1-pad6_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.pro b/src/SubcircuitLibrary/5_nand/5_nand.pro
new file mode 100644
index 00000000..b7d23f44
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_nand.pro
@@ -0,0 +1,83 @@
+update=Fri Jun 21 16:46:10 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=device
+LibName23=transistors
+LibName24=conn
+LibName25=linear
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_User
+LibName38=eSim_Plot
+LibName39=eSim_PSpice
+LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
+LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
+LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
+LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
+LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
+LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
+LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
+LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
+LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
+LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
+
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sch b/src/SubcircuitLibrary/5_nand/5_nand.sch
new file mode 100644
index 00000000..86379b08
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_nand.sch
@@ -0,0 +1,175 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+F 1 "5_and" H 4250 3850 60  0000 C CNN
+F 2 "" H 4150 3700 60  0000 C CNN
+F 3 "" H 4150 3700 60  0000 C CNN
+	1    4150 3700
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 5D0CBD97
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+F 2 "" H 5200 3650 60  0000 C CNN
+F 3 "" H 5200 3650 60  0000 C CNN
+	1    5150 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5D0CBDBE
+P 2900 2900
+F 0 "U1" H 2950 3000 30  0000 C CNN
+F 1 "PORT" H 2900 2900 30  0000 C CNN
+F 2 "" H 2900 2900 60  0000 C CNN
+F 3 "" H 2900 2900 60  0000 C CNN
+	1    2900 2900
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 2 1 5D0CBDF4
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+F 2 "" H 2900 3150 60  0000 C CNN
+F 3 "" H 2900 3150 60  0000 C CNN
+	2    2900 3150
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 3 1 5D0CBE16
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+F 2 "" H 2900 3400 60  0000 C CNN
+F 3 "" H 2900 3400 60  0000 C CNN
+	3    2900 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5D0CBE3F
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+F 1 "PORT" H 2900 3750 30  0000 C CNN
+F 2 "" H 2900 3750 60  0000 C CNN
+F 3 "" H 2900 3750 60  0000 C CNN
+	4    2900 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5D0CBE6B
+P 2900 4150
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+F 1 "PORT" H 2900 4150 30  0000 C CNN
+F 2 "" H 2900 4150 60  0000 C CNN
+F 3 "" H 2900 4150 60  0000 C CNN
+	5    2900 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5D0CBE9C
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+F 0 "U1" H 6250 3800 30  0000 C CNN
+F 1 "PORT" H 6200 3700 30  0000 C CNN
+F 2 "" H 6200 3700 60  0000 C CNN
+F 3 "" H 6200 3700 60  0000 C CNN
+	6    6200 3700
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	3150 2900 3700 2900
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	3350 4150 3350 3900
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	5450 3700 5950 3700
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sub b/src/SubcircuitLibrary/5_nand/5_nand.sub
new file mode 100644
index 00000000..c3e041fa
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_nand.sub
@@ -0,0 +1,12 @@
+* Subcircuit 5_nand
+.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
+.include 5_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
+* u2  net-_u2-pad1_ net-_u1-pad6_ d_inverter
+a1 net-_u2-pad1_ net-_u1-pad6_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_nand
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml
new file mode 100644
index 00000000..c4b4cde2
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/analysis b/src/SubcircuitLibrary/5_nand/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/5_nand/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file