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authorrahulp132020-02-21 12:36:46 +0530
committerrahulp132020-02-21 12:36:46 +0530
commit47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch)
tree55aefefe974f151de76c6a2dbe8df3b4c3393bbe /src/SubcircuitLibrary/5_nand
parent453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff)
downloadeSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz
eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2
eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip
restructured eSim libraries
Diffstat (limited to 'src/SubcircuitLibrary/5_nand')
-rw-r--r--src/SubcircuitLibrary/5_nand/3_and-cache.lib61
-rw-r--r--src/SubcircuitLibrary/5_nand/3_and.cir13
-rw-r--r--src/SubcircuitLibrary/5_nand/3_and.cir.out20
-rw-r--r--src/SubcircuitLibrary/5_nand/3_and.pro44
-rw-r--r--src/SubcircuitLibrary/5_nand/3_and.sch130
-rw-r--r--src/SubcircuitLibrary/5_nand/3_and.sub14
-rw-r--r--src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/5_nand/5_and-cache.lib79
-rw-r--r--src/SubcircuitLibrary/5_nand/5_and.cir14
-rw-r--r--src/SubcircuitLibrary/5_nand/5_and.cir.out22
-rw-r--r--src/SubcircuitLibrary/5_nand/5_and.pro50
-rw-r--r--src/SubcircuitLibrary/5_nand/5_and.sch171
-rw-r--r--src/SubcircuitLibrary/5_nand/5_and.sub16
-rw-r--r--src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/5_nand/5_nand-cache.lib78
-rw-r--r--src/SubcircuitLibrary/5_nand/5_nand.cir13
-rw-r--r--src/SubcircuitLibrary/5_nand/5_nand.cir.out18
-rw-r--r--src/SubcircuitLibrary/5_nand/5_nand.pro83
-rw-r--r--src/SubcircuitLibrary/5_nand/5_nand.sch175
-rw-r--r--src/SubcircuitLibrary/5_nand/5_nand.sub12
-rw-r--r--src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml1
-rw-r--r--src/SubcircuitLibrary/5_nand/analysis1
22 files changed, 0 insertions, 1017 deletions
diff --git a/src/SubcircuitLibrary/5_nand/3_and-cache.lib b/src/SubcircuitLibrary/5_nand/3_and-cache.lib
deleted file mode 100644
index 0a3ccf7f..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir b/src/SubcircuitLibrary/5_nand/3_and.cir
deleted file mode 100644
index 15f8954d..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir.out b/src/SubcircuitLibrary/5_nand/3_and.cir.out
deleted file mode 100644
index e3c96645..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/3_and.pro b/src/SubcircuitLibrary/5_nand/3_and.pro
deleted file mode 100644
index 0fdf4d25..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_nand/3_and.sch b/src/SubcircuitLibrary/5_nand/3_and.sch
deleted file mode 100644
index c853bf49..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nand/3_and.sub b/src/SubcircuitLibrary/5_nand/3_and.sub
deleted file mode 100644
index b949ae4f..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and \ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_and-cache.lib b/src/SubcircuitLibrary/5_nand/5_and-cache.lib
deleted file mode 100644
index 4cf915be..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir b/src/SubcircuitLibrary/5_nand/5_and.cir
deleted file mode 100644
index ca1199bd..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
-U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
-U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir.out b/src/SubcircuitLibrary/5_nand/5_and.cir.out
deleted file mode 100644
index 20d3f8a5..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.cir.out
+++ /dev/null
@@ -1,22 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_and.pro b/src/SubcircuitLibrary/5_nand/5_and.pro
deleted file mode 100644
index a9d6304f..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.pro
+++ /dev/null
@@ -1,50 +0,0 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
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-version=1
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-LibName8=eSim_Devices
-LibName9=eSim_Digital
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-LibName13=eSim_Power
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-LibName15=eSim_Sources
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-LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/5_nand/5_and.sch b/src/SubcircuitLibrary/5_nand/5_and.sch
deleted file mode 100644
index 0d86cdec..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.sch
+++ /dev/null
@@ -1,171 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
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diff --git a/src/SubcircuitLibrary/5_nand/5_and.sub b/src/SubcircuitLibrary/5_nand/5_and.sub
deleted file mode 100644
index 9d929fcb..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.sub
+++ /dev/null
@@ -1,16 +0,0 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and \ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml
deleted file mode 100644
index ae2c08a7..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib b/src/SubcircuitLibrary/5_nand/5_nand-cache.lib
deleted file mode 100644
index cb517be1..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib
+++ /dev/null
@@ -1,78 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_and" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir b/src/SubcircuitLibrary/5_nand/5_nand.cir
deleted file mode 100644
index e833d0f4..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and
-U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir.out b/src/SubcircuitLibrary/5_nand/5_nand.cir.out
deleted file mode 100644
index 164de911..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
-
-.include 5_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
-* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 net-_u2-pad1_ net-_u1-pad6_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.pro b/src/SubcircuitLibrary/5_nand/5_nand.pro
deleted file mode 100644
index b7d23f44..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.pro
+++ /dev/null
@@ -1,83 +0,0 @@
-update=Fri Jun 21 16:46:10 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
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-ModuleTextSizeV=1.000000000000
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-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
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-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
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-LibName4=microcontrollers
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-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
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-LibName18=opto
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-LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sch b/src/SubcircuitLibrary/5_nand/5_nand.sch
deleted file mode 100644
index 86379b08..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.sch
+++ /dev/null
@@ -1,175 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
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-LIBS:microcontrollers
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- 3250 3750 3150 3750
-Wire Wire Line
- 3150 4150 3350 4150
-Wire Wire Line
- 3350 4150 3350 3900
-Wire Wire Line
- 3350 3900 3700 3900
-Wire Wire Line
- 4700 3700 4850 3700
-Wire Wire Line
- 5450 3700 5950 3700
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sub b/src/SubcircuitLibrary/5_nand/5_nand.sub
deleted file mode 100644
index c3e041fa..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 5_nand
-.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
-.include 5_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
-* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter
-a1 net-_u2-pad1_ net-_u1-pad6_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_nand \ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml
deleted file mode 100644
index c4b4cde2..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice> \ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/analysis b/src/SubcircuitLibrary/5_nand/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/5_nand/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00 \ No newline at end of file