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authornilshah982019-07-02 16:42:20 +0530
committernilshah982019-07-02 16:46:12 +0530
commitb085a3df519debbc99acf4ded7e118a1690d6665 (patch)
tree0fc3e5389c2a77a97d1a065875fe87ddee2c23f4 /src/SubcircuitLibrary/5_nand/5_nand.sub
parente7cd941bc4a48ff8684e4db6b9dff0efeb51fa6e (diff)
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Subcircuit added by ECE fellows 2019
Diffstat (limited to 'src/SubcircuitLibrary/5_nand/5_nand.sub')
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+* Subcircuit 5_nand
+.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
+* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
+.include 5_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
+* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter
+a1 net-_u2-pad1_ net-_u1-pad6_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_nand \ No newline at end of file