common code for Win and Linux, merged py2 changes

12 files changed, 632 insertions, 632 deletions

diff --git a/src/SubcircuitLibrary/5_and/3_and-cache.lib b/src/SubcircuitLibrary/5_and/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/5_and/3_and-cache.lib
+++ b/src/SubcircuitLibrary/5_and/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3

-#encoding utf-8

-#

-# PORT

-#

-DEF PORT U 0 40 Y Y 26 F N

-F0 "U" 50 100 30 H V C CNN

-F1 "PORT" 0 0 30 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0

-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50

-S -100 50 100 -50 0 1 0 N

-X ~ 1 250 0 100 L 30 30 1 1 B

-X ~ 2 250 0 100 L 30 30 2 1 B

-X ~ 3 250 0 100 L 30 30 3 1 B

-X ~ 4 250 0 100 L 30 30 4 1 B

-X ~ 5 250 0 100 L 30 30 5 1 B

-X ~ 6 250 0 100 L 30 30 6 1 B

-X ~ 7 250 0 100 L 30 30 7 1 B

-X ~ 8 250 0 100 L 30 30 8 1 B

-X ~ 9 250 0 100 L 30 30 9 1 B

-X ~ 10 250 0 100 L 30 30 10 1 B

-X ~ 11 250 0 100 L 30 30 11 1 B

-X ~ 12 250 0 100 L 30 30 12 1 B

-X ~ 13 250 0 100 L 30 30 13 1 B

-X ~ 14 250 0 100 L 30 30 14 1 B

-X ~ 15 250 0 100 L 30 30 15 1 B

-X ~ 16 250 0 100 L 30 30 16 1 B

-X ~ 17 250 0 100 L 30 30 17 1 B

-X ~ 18 250 0 100 L 30 30 18 1 B

-X ~ 19 250 0 100 L 30 30 19 1 B

-X ~ 20 250 0 100 L 30 30 20 1 B

-X ~ 21 250 0 100 L 30 30 21 1 B

-X ~ 22 250 0 100 L 30 30 22 1 B

-X ~ 23 250 0 100 L 30 30 23 1 B

-X ~ 24 250 0 100 L 30 30 24 1 B

-X ~ 25 250 0 100 L 30 30 25 1 B

-X ~ 26 250 0 100 L 30 30 26 1 B

-ENDDRAW

-ENDDEF

-#

-# d_and

-#

-DEF d_and U 0 40 Y Y 1 F N

-F0 "U" 0 0 60 H V C CNN

-F1 "d_and" 50 100 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50

-A 150 49 100 6 900 0 1 0 N 250 50 150 150

-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N

-X IN1 1 -450 100 200 R 50 50 1 1 I

-X IN2 2 -450 0 200 R 50 50 1 1 I

-X OUT 3 450 50 200 L 50 50 1 1 O

-ENDDRAW

-ENDDEF

-#

-#End Library

+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/5_and/3_and.cir b/src/SubcircuitLibrary/5_and/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/5_and/3_and.cir
+++ b/src/SubcircuitLibrary/5_and/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir

-

-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57

-

-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N

-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

-

-* Sheet Name: /

-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		

-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		

-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		

-

-.end

+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/5_and/3_and.cir.out b/src/SubcircuitLibrary/5_and/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/5_and/3_and.cir.out
+++ b/src/SubcircuitLibrary/5_and/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir

-

-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and

-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and

-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port

-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2

-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-.tran 0e-00 0e-00 0e-00

-

-* Control Statements 

-.control

-run

-print allv > plot_data_v.txt

-print alli > plot_data_i.txt

-.endc

-.end

+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/5_and/3_and.pro b/src/SubcircuitLibrary/5_and/3_and.pro
index 0fdf4d25..76df4655 100644
--- a/src/SubcircuitLibrary/5_and/3_and.pro
+++ b/src/SubcircuitLibrary/5_and/3_and.pro
@@ -1,44 +1,44 @@
-update=05/31/19 15:26:09

-version=1

-last_client=eeschema

-[general]

-version=1

-RootSch=

-BoardNm=

-[pcbnew]

-version=1

-LastNetListRead=

-UseCmpFile=1

-PadDrill=0.600000000000

-PadDrillOvalY=0.600000000000

-PadSizeH=1.500000000000

-PadSizeV=1.500000000000

-PcbTextSizeV=1.500000000000

-PcbTextSizeH=1.500000000000

-PcbTextThickness=0.300000000000

-ModuleTextSizeV=1.000000000000

-ModuleTextSizeH=1.000000000000

-ModuleTextSizeThickness=0.150000000000

-SolderMaskClearance=0.000000000000

-SolderMaskMinWidth=0.000000000000

-DrawSegmentWidth=0.200000000000

-BoardOutlineThickness=0.100000000000

-ModuleOutlineThickness=0.150000000000

-[cvpcb]

-version=1

-NetIExt=net

-[eeschema]

-version=1

-LibDir=../../../kicadSchematicLibrary

-[eeschema/libraries]

-LibName1=eSim_Analog

-LibName2=eSim_Devices

-LibName3=eSim_Digital

-LibName4=eSim_Hybrid

-LibName5=eSim_Miscellaneous

-LibName6=eSim_Plot

-LibName7=eSim_Power

-LibName8=eSim_PSpice

-LibName9=eSim_Sources

-LibName10=eSim_Subckt

-LibName11=eSim_User

+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_and/3_and.sch b/src/SubcircuitLibrary/5_and/3_and.sch
index c853bf49..d6ac89f9 100644
--- a/src/SubcircuitLibrary/5_and/3_and.sch
+++ b/src/SubcircuitLibrary/5_and/3_and.sch
@@ -1,130 +1,130 @@
-EESchema Schematic File Version 2

-LIBS:power

-LIBS:texas

-LIBS:intel

-LIBS:audio

-LIBS:interface

-LIBS:digital-audio

-LIBS:philips

-LIBS:display

-LIBS:cypress

-LIBS:siliconi

-LIBS:opto

-LIBS:atmel

-LIBS:contrib

-LIBS:valves

-LIBS:eSim_Analog

-LIBS:eSim_Devices

-LIBS:eSim_Digital

-LIBS:eSim_Hybrid

-LIBS:eSim_Miscellaneous

-LIBS:eSim_Plot

-LIBS:eSim_Power

-LIBS:eSim_PSpice

-LIBS:eSim_Sources

-LIBS:eSim_Subckt

-LIBS:eSim_User

-LIBS:3_and-cache

-EELAYER 25 0

-EELAYER END

-$Descr A4 11693 8268

-encoding utf-8

-Sheet 1 1

-Title ""

-Date ""

-Rev ""

-Comp ""

-Comment1 ""

-Comment2 ""

-Comment3 ""

-Comment4 ""

-$EndDescr

-$Comp

-L d_and U2

-U 1 1 5C9A24D8

-P 4250 2700

-F 0 "U2" H 4250 2700 60  0000 C CNN

-F 1 "d_and" H 4300 2800 60  0000 C CNN

-F 2 "" H 4250 2700 60  0000 C CNN

-F 3 "" H 4250 2700 60  0000 C CNN

-	1    4250 2700

-	1    0    0    -1  

-$EndComp

-$Comp

-L d_and U3

-U 1 1 5C9A2538

-P 5150 2900

-F 0 "U3" H 5150 2900 60  0000 C CNN

-F 1 "d_and" H 5200 3000 60  0000 C CNN

-F 2 "" H 5150 2900 60  0000 C CNN

-F 3 "" H 5150 2900 60  0000 C CNN

-	1    5150 2900

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 1 1 5C9A259A

-P 3050 2600

-F 0 "U1" H 3100 2700 30  0000 C CNN

-F 1 "PORT" H 3050 2600 30  0000 C CNN

-F 2 "" H 3050 2600 60  0000 C CNN

-F 3 "" H 3050 2600 60  0000 C CNN

-	1    3050 2600

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 2 1 5C9A25D9

-P 3050 2800

-F 0 "U1" H 3100 2900 30  0000 C CNN

-F 1 "PORT" H 3050 2800 30  0000 C CNN

-F 2 "" H 3050 2800 60  0000 C CNN

-F 3 "" H 3050 2800 60  0000 C CNN

-	2    3050 2800

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 3 1 5C9A260A

-P 3050 3100

-F 0 "U1" H 3100 3200 30  0000 C CNN

-F 1 "PORT" H 3050 3100 30  0000 C CNN

-F 2 "" H 3050 3100 60  0000 C CNN

-F 3 "" H 3050 3100 60  0000 C CNN

-	3    3050 3100

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 4 1 5C9A2637

-P 6900 2850

-F 0 "U1" H 6950 2950 30  0000 C CNN

-F 1 "PORT" H 6900 2850 30  0000 C CNN

-F 2 "" H 6900 2850 60  0000 C CNN

-F 3 "" H 6900 2850 60  0000 C CNN

-	4    6900 2850

-	-1   0    0    1   

-$EndComp

-Wire Wire Line

-	4700 2650 4700 2800

-Wire Wire Line

-	5600 2850 6650 2850

-Wire Wire Line

-	3800 2600 3300 2600

-Wire Wire Line

-	3800 2700 3300 2700

-Wire Wire Line

-	3300 2700 3300 2800

-Wire Wire Line

-	3300 3100 4700 3100

-Wire Wire Line

-	4700 3100 4700 2900

-Text Notes 3500 2600 0    60   ~ 12

-in1

-Text Notes 3450 2800 0    60   ~ 12

-in2\n

-Text Notes 3500 3100 0    60   ~ 12

-in3

-Text Notes 6100 2850 0    60   ~ 12

-out

-$EndSCHEMATC

+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_and/3_and.sub b/src/SubcircuitLibrary/5_and/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/5_and/3_and.sub
+++ b/src/SubcircuitLibrary/5_and/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and

-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 

-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir

-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and

-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and

-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2

-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

-* Control Statements

-

+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/5_and-cache.lib b/src/SubcircuitLibrary/5_and/5_and-cache.lib
index 4cf915be..ac396288 100644
--- a/src/SubcircuitLibrary/5_and/5_and-cache.lib
+++ b/src/SubcircuitLibrary/5_and/5_and-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3

-#encoding utf-8

-#

-# 3_and

-#

-DEF 3_and X 0 40 Y Y 1 F N

-F0 "X" 900 300 60 H V C CNN

-F1 "3_and" 950 500 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250

-P 2 0 1 0  650 550  1000 550 N

-P 3 0 1 0  650 550  650 250  1000 250 N

-X in1 1 450 500 200 R 50 50 1 1 I

-X in2 2 450 400 200 R 50 50 1 1 I

-X in3 3 450 300 200 R 50 50 1 1 I

-X out 4 1300 400 200 L 50 50 1 1 O

-ENDDRAW

-ENDDEF

-#

-# PORT

-#

-DEF PORT U 0 40 Y Y 26 F N

-F0 "U" 50 100 30 H V C CNN

-F1 "PORT" 0 0 30 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0

-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50

-S -100 50 100 -50 0 1 0 N

-X ~ 1 250 0 100 L 30 30 1 1 B

-X ~ 2 250 0 100 L 30 30 2 1 B

-X ~ 3 250 0 100 L 30 30 3 1 B

-X ~ 4 250 0 100 L 30 30 4 1 B

-X ~ 5 250 0 100 L 30 30 5 1 B

-X ~ 6 250 0 100 L 30 30 6 1 B

-X ~ 7 250 0 100 L 30 30 7 1 B

-X ~ 8 250 0 100 L 30 30 8 1 B

-X ~ 9 250 0 100 L 30 30 9 1 B

-X ~ 10 250 0 100 L 30 30 10 1 B

-X ~ 11 250 0 100 L 30 30 11 1 B

-X ~ 12 250 0 100 L 30 30 12 1 B

-X ~ 13 250 0 100 L 30 30 13 1 B

-X ~ 14 250 0 100 L 30 30 14 1 B

-X ~ 15 250 0 100 L 30 30 15 1 B

-X ~ 16 250 0 100 L 30 30 16 1 B

-X ~ 17 250 0 100 L 30 30 17 1 B

-X ~ 18 250 0 100 L 30 30 18 1 B

-X ~ 19 250 0 100 L 30 30 19 1 B

-X ~ 20 250 0 100 L 30 30 20 1 B

-X ~ 21 250 0 100 L 30 30 21 1 B

-X ~ 22 250 0 100 L 30 30 22 1 B

-X ~ 23 250 0 100 L 30 30 23 1 B

-X ~ 24 250 0 100 L 30 30 24 1 B

-X ~ 25 250 0 100 L 30 30 25 1 B

-X ~ 26 250 0 100 L 30 30 26 1 B

-ENDDRAW

-ENDDEF

-#

-# d_and

-#

-DEF d_and U 0 40 Y Y 1 F N

-F0 "U" 0 0 60 H V C CNN

-F1 "d_and" 50 100 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50

-A 150 49 100 6 900 0 1 0 N 250 50 150 150

-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N

-X IN1 1 -450 100 200 R 50 50 1 1 I

-X IN2 2 -450 0 200 R 50 50 1 1 I

-X OUT 3 450 50 200 L 50 50 1 1 O

-ENDDRAW

-ENDDEF

-#

-#End Library

+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/5_and/5_and.cir b/src/SubcircuitLibrary/5_and/5_and.cir
index ca1199bd..6a05b9b5 100644
--- a/src/SubcircuitLibrary/5_and/5_and.cir
+++ b/src/SubcircuitLibrary/5_and/5_and.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir

-

-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13

-

-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N

-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

-

-* Sheet Name: /

-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		

-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		

-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		

-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		

-

-.end

+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/5_and/5_and.cir.out b/src/SubcircuitLibrary/5_and/5_and.cir.out
index 20d3f8a5..6a6b126a 100644
--- a/src/SubcircuitLibrary/5_and/5_and.cir.out
+++ b/src/SubcircuitLibrary/5_and/5_and.cir.out
@@ -1,22 +1,22 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir

-

-.include 3_and.sub

-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and

-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and

-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and

-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port

-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2

-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-.tran 0e-00 0e-00 0e-00

-

-* Control Statements 

-.control

-run

-print allv > plot_data_v.txt

-print alli > plot_data_i.txt

-.endc

-.end

+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/5_and/5_and.pro b/src/SubcircuitLibrary/5_and/5_and.pro
index a9d6304f..7a2f090e 100644
--- a/src/SubcircuitLibrary/5_and/5_and.pro
+++ b/src/SubcircuitLibrary/5_and/5_and.pro
@@ -1,50 +1,50 @@
-update=06/01/19 11:31:03

-version=1

-last_client=eeschema

-[general]

-version=1

-RootSch=

-BoardNm=

-[pcbnew]

-version=1

-LastNetListRead=

-UseCmpFile=1

-PadDrill=0.600000000000

-PadDrillOvalY=0.600000000000

-PadSizeH=1.500000000000

-PadSizeV=1.500000000000

-PcbTextSizeV=1.500000000000

-PcbTextSizeH=1.500000000000

-PcbTextThickness=0.300000000000

-ModuleTextSizeV=1.000000000000

-ModuleTextSizeH=1.000000000000

-ModuleTextSizeThickness=0.150000000000

-SolderMaskClearance=0.000000000000

-SolderMaskMinWidth=0.000000000000

-DrawSegmentWidth=0.200000000000

-BoardOutlineThickness=0.100000000000

-ModuleOutlineThickness=0.150000000000

-[cvpcb]

-version=1

-NetIExt=net

-[eeschema]

-version=1

-LibDir=../../../kicadSchematicLibrary

-[eeschema/libraries]

-LibName1=cypress

-LibName2=siliconi

-LibName3=opto

-LibName4=atmel

-LibName5=contrib

-LibName6=valves

-LibName7=eSim_Analog

-LibName8=eSim_Devices

-LibName9=eSim_Digital

-LibName10=eSim_Hybrid

-LibName11=eSim_Miscellaneous

-LibName12=eSim_Plot

-LibName13=eSim_Power

-LibName14=eSim_PSpice

-LibName15=eSim_Sources

-LibName16=eSim_Subckt

-LibName17=eSim_User

+update=06/01/19 11:31:03
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_PSpice
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
+LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/5_and/5_and.sch b/src/SubcircuitLibrary/5_and/5_and.sch
index 0d86cdec..e9eb58ee 100644
--- a/src/SubcircuitLibrary/5_and/5_and.sch
+++ b/src/SubcircuitLibrary/5_and/5_and.sch
@@ -1,171 +1,171 @@
-EESchema Schematic File Version 2

-LIBS:cypress

-LIBS:siliconi

-LIBS:opto

-LIBS:atmel

-LIBS:contrib

-LIBS:valves

-LIBS:eSim_Analog

-LIBS:eSim_Devices

-LIBS:eSim_Digital

-LIBS:eSim_Hybrid

-LIBS:eSim_Miscellaneous

-LIBS:eSim_Plot

-LIBS:eSim_Power

-LIBS:eSim_PSpice

-LIBS:eSim_Sources

-LIBS:eSim_Subckt

-LIBS:eSim_User

-LIBS:5_and-cache

-EELAYER 25 0

-EELAYER END

-$Descr A4 11693 8268

-encoding utf-8

-Sheet 1 1

-Title ""

-Date ""

-Rev ""

-Comp ""

-Comment1 ""

-Comment2 ""

-Comment3 ""

-Comment4 ""

-$EndDescr

-$Comp

-L 3_and X1

-U 1 1 5C9A2741

-P 3800 3350

-F 0 "X1" H 4700 3650 60  0000 C CNN

-F 1 "3_and" H 4750 3850 60  0000 C CNN

-F 2 "" H 3800 3350 60  0000 C CNN

-F 3 "" H 3800 3350 60  0000 C CNN

-	1    3800 3350

-	1    0    0    -1  

-$EndComp

-$Comp

-L d_and U2

-U 1 1 5C9A2764

-P 4650 3400

-F 0 "U2" H 4650 3400 60  0000 C CNN

-F 1 "d_and" H 4700 3500 60  0000 C CNN

-F 2 "" H 4650 3400 60  0000 C CNN

-F 3 "" H 4650 3400 60  0000 C CNN

-	1    4650 3400

-	1    0    0    -1  

-$EndComp

-$Comp

-L d_and U3

-U 1 1 5C9A2791

-P 5550 3200

-F 0 "U3" H 5550 3200 60  0000 C CNN

-F 1 "d_and" H 5600 3300 60  0000 C CNN

-F 2 "" H 5550 3200 60  0000 C CNN

-F 3 "" H 5550 3200 60  0000 C CNN

-	1    5550 3200

-	1    0    0    -1  

-$EndComp

-Wire Wire Line

-	5100 3100 5100 2950

-Wire Wire Line

-	5100 3200 5100 3350

-Wire Wire Line

-	4250 2850 4250 2700

-Wire Wire Line

-	4250 2700 3600 2700

-Wire Wire Line

-	4250 2950 4150 2950

-Wire Wire Line

-	4150 2950 4150 2900

-Wire Wire Line

-	4150 2900 3600 2900

-Wire Wire Line

-	4200 3300 3600 3300

-Wire Wire Line

-	4250 3050 4250 3100

-Wire Wire Line

-	4250 3100 3600 3100

-Wire Wire Line

-	4200 3400 4200 3500

-Wire Wire Line

-	4200 3500 3600 3500

-Wire Wire Line

-	6000 3150 6500 3150

-$Comp

-L PORT U1

-U 1 1 5C9A2865

-P 3350 2700

-F 0 "U1" H 3400 2800 30  0000 C CNN

-F 1 "PORT" H 3350 2700 30  0000 C CNN

-F 2 "" H 3350 2700 60  0000 C CNN

-F 3 "" H 3350 2700 60  0000 C CNN

-	1    3350 2700

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 2 1 5C9A28B6

-P 3350 2900

-F 0 "U1" H 3400 3000 30  0000 C CNN

-F 1 "PORT" H 3350 2900 30  0000 C CNN

-F 2 "" H 3350 2900 60  0000 C CNN

-F 3 "" H 3350 2900 60  0000 C CNN

-	2    3350 2900

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 3 1 5C9A28D9

-P 3350 3100

-F 0 "U1" H 3400 3200 30  0000 C CNN

-F 1 "PORT" H 3350 3100 30  0000 C CNN

-F 2 "" H 3350 3100 60  0000 C CNN

-F 3 "" H 3350 3100 60  0000 C CNN

-	3    3350 3100

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 4 1 5C9A28FF

-P 3350 3300

-F 0 "U1" H 3400 3400 30  0000 C CNN

-F 1 "PORT" H 3350 3300 30  0000 C CNN

-F 2 "" H 3350 3300 60  0000 C CNN

-F 3 "" H 3350 3300 60  0000 C CNN

-	4    3350 3300

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 5 1 5C9A2928

-P 3350 3500

-F 0 "U1" H 3400 3600 30  0000 C CNN

-F 1 "PORT" H 3350 3500 30  0000 C CNN

-F 2 "" H 3350 3500 60  0000 C CNN

-F 3 "" H 3350 3500 60  0000 C CNN

-	5    3350 3500

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 6 1 5C9A2958

-P 6750 3150

-F 0 "U1" H 6800 3250 30  0000 C CNN

-F 1 "PORT" H 6750 3150 30  0000 C CNN

-F 2 "" H 6750 3150 60  0000 C CNN

-F 3 "" H 6750 3150 60  0000 C CNN

-	6    6750 3150

-	-1   0    0    1   

-$EndComp

-Text Notes 3800 2700 0    60   ~ 12

-in1

-Text Notes 3800 2900 0    60   ~ 12

-in2

-Text Notes 3800 3100 0    60   ~ 12

-in3

-Text Notes 3800 3300 0    60   ~ 12

-in4

-Text Notes 3800 3500 0    60   ~ 12

-in5

-Text Notes 6150 3150 0    60   ~ 12

-out

-$EndSCHEMATC

+EESchema Schematic File Version 2
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_and/5_and.sub b/src/SubcircuitLibrary/5_and/5_and.sub
index 9d929fcb..35b10e17 100644
--- a/src/SubcircuitLibrary/5_and/5_and.sub
+++ b/src/SubcircuitLibrary/5_and/5_and.sub
@@ -1,16 +1,16 @@
-* Subcircuit 5_and

-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 

-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir

-.include 3_and.sub

-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and

-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and

-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and

-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2

-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

-* Schematic Name: d_and, NgSpice Name: d_and

-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

-* Control Statements

-

+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 5_and
\ No newline at end of file