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authorfossee2019-08-29 12:03:11 +0530
committerfossee2019-08-29 12:03:11 +0530
commitfe3bd934634bb2dae1cadf35e7c6d59facbedf66 (patch)
treeab841ad9ca3d56f7eb85cb3650f6608b80656027 /src/SubcircuitLibrary/4_and/4_and.cir.out
parentf7567ac99f21fb6c87d60f309f0aa71dee6ae975 (diff)
downloadeSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.tar.gz
eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.tar.bz2
eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.zip
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+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end