Merge pull request #132 from rahulp13/master

major changes

8 files changed, 0 insertions, 316 deletions

diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
deleted file mode 100644
index a3c1c972..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3

-#encoding utf-8

-#

-# PORT

-#

-DEF PORT U 0 40 Y Y 26 F N

-F0 "U" 50 100 30 H V C CNN

-F1 "PORT" 0 0 30 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0

-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50

-S -100 50 100 -50 0 1 0 N

-X ~ 1 250 0 100 L 30 30 1 1 B

-X ~ 2 250 0 100 L 30 30 2 1 B

-X ~ 3 250 0 100 L 30 30 3 1 B

-X ~ 4 250 0 100 L 30 30 4 1 B

-X ~ 5 250 0 100 L 30 30 5 1 B

-X ~ 6 250 0 100 L 30 30 6 1 B

-X ~ 7 250 0 100 L 30 30 7 1 B

-X ~ 8 250 0 100 L 30 30 8 1 B

-X ~ 9 250 0 100 L 30 30 9 1 B

-X ~ 10 250 0 100 L 30 30 10 1 B

-X ~ 11 250 0 100 L 30 30 11 1 B

-X ~ 12 250 0 100 L 30 30 12 1 B

-X ~ 13 250 0 100 L 30 30 13 1 B

-X ~ 14 250 0 100 L 30 30 14 1 B

-X ~ 15 250 0 100 L 30 30 15 1 B

-X ~ 16 250 0 100 L 30 30 16 1 B

-X ~ 17 250 0 100 L 30 30 17 1 B

-X ~ 18 250 0 100 L 30 30 18 1 B

-X ~ 19 250 0 100 L 30 30 19 1 B

-X ~ 20 250 0 100 L 30 30 20 1 B

-X ~ 21 250 0 100 L 30 30 21 1 B

-X ~ 22 250 0 100 L 30 30 22 1 B

-X ~ 23 250 0 100 L 30 30 23 1 B

-X ~ 24 250 0 100 L 30 30 24 1 B

-X ~ 25 250 0 100 L 30 30 25 1 B

-X ~ 26 250 0 100 L 30 30 26 1 B

-ENDDRAW

-ENDDEF

-#

-# d_or

-#

-DEF d_or U 0 40 Y Y 1 F N

-F0 "U" 0 0 60 H V C CNN

-F1 "d_or" 0 100 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50

-A -25 -124 325 574 323 0 1 0 N 150 150 250 50

-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50

-P 2 0 1 0  -250 -50  150 -50 N

-P 2 0 1 0  -250 150  150 150 N

-X IN1 1 -450 100 215 R 50 50 1 1 I

-X IN2 2 -450 0 215 R 50 50 1 1 I

-X OUT 3 450 50 200 L 50 50 1 1 O

-ENDDRAW

-ENDDEF

-#

-#End Library

diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir
deleted file mode 100644
index 7adbf177..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir

-

-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12

-

-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N

-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

-

-* Sheet Name: /

-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		

-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		

-U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		

-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		

-

-.end

diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out
deleted file mode 100644
index 4388b975..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir.out
+++ /dev/null
@@ -1,24 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir

-

-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or

-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or

-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or

-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port

-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2

-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3

-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4

-* Schematic Name: d_or, NgSpice Name: d_or

-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_or, NgSpice Name: d_or

-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-* Schematic Name: d_or, NgSpice Name: d_or

-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 

-.tran 0e-00 0e-00 0e-00

-

-* Control Statements 

-.control

-run

-print allv > plot_data_v.txt

-print alli > plot_data_i.txt

-.endc

-.end

diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro
deleted file mode 100644
index 1e19b3a7..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=06/01/19 12:36:09

-version=1

-last_client=eeschema

-[general]

-version=1

-RootSch=

-BoardNm=

-[pcbnew]

-version=1

-LastNetListRead=

-UseCmpFile=1

-PadDrill=0.600000000000

-PadDrillOvalY=0.600000000000

-PadSizeH=1.500000000000

-PadSizeV=1.500000000000

-PcbTextSizeV=1.500000000000

-PcbTextSizeH=1.500000000000

-PcbTextThickness=0.300000000000

-ModuleTextSizeV=1.000000000000

-ModuleTextSizeH=1.000000000000

-ModuleTextSizeThickness=0.150000000000

-SolderMaskClearance=0.000000000000

-SolderMaskMinWidth=0.000000000000

-DrawSegmentWidth=0.200000000000

-BoardOutlineThickness=0.100000000000

-ModuleOutlineThickness=0.150000000000

-[cvpcb]

-version=1

-NetIExt=net

-[eeschema]

-version=1

-LibDir=../../../kicadSchematicLibrary

-[eeschema/libraries]

-LibName1=power

-LibName2=eSim_Analog

-LibName3=eSim_Devices

-LibName4=eSim_Digital

-LibName5=eSim_Hybrid

-LibName6=eSim_Miscellaneous

-LibName7=eSim_Plot

-LibName8=eSim_Power

-LibName9=eSim_PSpice

-LibName10=eSim_Sources

-LibName11=eSim_Subckt

-LibName12=eSim_User

diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch
deleted file mode 100644
index 2f28896c..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.sch
+++ /dev/null
@@ -1,150 +0,0 @@
-EESchema Schematic File Version 2

-LIBS:power

-LIBS:eSim_Analog

-LIBS:eSim_Devices

-LIBS:eSim_Digital

-LIBS:eSim_Hybrid

-LIBS:eSim_Miscellaneous

-LIBS:eSim_Plot

-LIBS:eSim_Power

-LIBS:eSim_PSpice

-LIBS:eSim_Sources

-LIBS:eSim_Subckt

-LIBS:eSim_User

-EELAYER 25 0

-EELAYER END

-$Descr A4 11693 8268

-encoding utf-8

-Sheet 1 1

-Title ""

-Date ""

-Rev ""

-Comp ""

-Comment1 ""

-Comment2 ""

-Comment3 ""

-Comment4 ""

-$EndDescr

-$Comp

-L d_or U2

-U 1 1 5C9D00E1

-P 4300 2950

-F 0 "U2" H 4300 2950 60  0000 C CNN

-F 1 "d_or" H 4300 3050 60  0000 C CNN

-F 2 "" H 4300 2950 60  0000 C CNN

-F 3 "" H 4300 2950 60  0000 C CNN

-	1    4300 2950

-	1    0    0    -1  

-$EndComp

-$Comp

-L d_or U3

-U 1 1 5C9D011F

-P 4300 3350

-F 0 "U3" H 4300 3350 60  0000 C CNN

-F 1 "d_or" H 4300 3450 60  0000 C CNN

-F 2 "" H 4300 3350 60  0000 C CNN

-F 3 "" H 4300 3350 60  0000 C CNN

-	1    4300 3350

-	1    0    0    -1  

-$EndComp

-$Comp

-L d_or U4

-U 1 1 5C9D0141

-P 5250 3150

-F 0 "U4" H 5250 3150 60  0000 C CNN

-F 1 "d_or" H 5250 3250 60  0000 C CNN

-F 2 "" H 5250 3150 60  0000 C CNN

-F 3 "" H 5250 3150 60  0000 C CNN

-	1    5250 3150

-	1    0    0    -1  

-$EndComp

-Wire Wire Line

-	4800 3050 4800 2900

-Wire Wire Line

-	4800 2900 4750 2900

-Wire Wire Line

-	4800 3150 4800 3300

-Wire Wire Line

-	4800 3300 4750 3300

-Wire Wire Line

-	3350 2850 3850 2850

-Wire Wire Line

-	3850 2950 3600 2950

-Wire Wire Line

-	3850 3250 3350 3250

-Wire Wire Line

-	3600 2950 3600 3000

-Wire Wire Line

-	3600 3000 3350 3000

-Wire Wire Line

-	3850 3350 3850 3400

-Wire Wire Line

-	3850 3400 3350 3400

-Wire Wire Line

-	5700 3100 6200 3100

-$Comp

-L PORT U1

-U 1 1 5C9D01F4

-P 3100 2850

-F 0 "U1" H 3150 2950 30  0000 C CNN

-F 1 "PORT" H 3100 2850 30  0000 C CNN

-F 2 "" H 3100 2850 60  0000 C CNN

-F 3 "" H 3100 2850 60  0000 C CNN

-	1    3100 2850

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 2 1 5C9D022F

-P 3100 3000

-F 0 "U1" H 3150 3100 30  0000 C CNN

-F 1 "PORT" H 3100 3000 30  0000 C CNN

-F 2 "" H 3100 3000 60  0000 C CNN

-F 3 "" H 3100 3000 60  0000 C CNN

-	2    3100 3000

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 3 1 5C9D0271

-P 3100 3250

-F 0 "U1" H 3150 3350 30  0000 C CNN

-F 1 "PORT" H 3100 3250 30  0000 C CNN

-F 2 "" H 3100 3250 60  0000 C CNN

-F 3 "" H 3100 3250 60  0000 C CNN

-	3    3100 3250

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 4 1 5C9D0299

-P 3100 3400

-F 0 "U1" H 3150 3500 30  0000 C CNN

-F 1 "PORT" H 3100 3400 30  0000 C CNN

-F 2 "" H 3100 3400 60  0000 C CNN

-F 3 "" H 3100 3400 60  0000 C CNN

-	4    3100 3400

-	1    0    0    -1  

-$EndComp

-$Comp

-L PORT U1

-U 5 1 5C9D02C2

-P 6450 3100

-F 0 "U1" H 6500 3200 30  0000 C CNN

-F 1 "PORT" H 6450 3100 30  0000 C CNN

-F 2 "" H 6450 3100 60  0000 C CNN

-F 3 "" H 6450 3100 60  0000 C CNN

-	5    6450 3100

-	-1   0    0    1   

-$EndComp

-Text Notes 3450 2850 0    60   ~ 12

-in1

-Text Notes 3450 3000 0    60   ~ 12

-in2

-Text Notes 3450 3250 0    60   ~ 12

-in3

-Text Notes 3450 3400 0    60   ~ 12

-in4

-Text Notes 5800 3100 0    60   ~ 12

-out

-$EndSCHEMATC

diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub
deleted file mode 100644
index 53fc8b33..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit 4_OR

-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 

-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir

-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or

-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or

-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or

-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2

-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3

-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4

-* Schematic Name: d_or, NgSpice Name: d_or

-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

-* Schematic Name: d_or, NgSpice Name: d_or

-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

-* Schematic Name: d_or, NgSpice Name: d_or

-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )

-* Control Statements

-

-.ends 4_OR
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml
deleted file mode 100644
index 0683d9eb..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_OR/analysis b/src/SubcircuitLibrary/4_OR/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4_OR/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file