common code for Win and Linux, merged py2 changes

9 files changed, 908 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/4017/4017-cache.lib b/src/SubcircuitLibrary/4017/4017-cache.lib
new file mode 100644
index 00000000..efa6746f
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4017/4017.cir b/src/SubcircuitLibrary/4017/4017.cir
new file mode 100644
index 00000000..67ac9971
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.cir
@@ -0,0 +1,26 @@
+* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7  Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff		
+U11  Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff		
+U15  Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff		
+U19  Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff		
+U22  Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
+U2  Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and		
+U3  Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and		
+U4  Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and		
+U5  Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and		
+U6  Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and		
+U8  Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and		
+U9  Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and		
+U12  Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and		
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and		
+
+.end
diff --git a/src/SubcircuitLibrary/4017/4017.cir.out b/src/SubcircuitLibrary/4017/4017.cir.out
new file mode 100644
index 00000000..e3a384c5
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.cir.out
@@ -0,0 +1,72 @@
+* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir
+
+* u7  net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff
+* u11  net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff
+* u15  net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff
+* u19  net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff
+* u22  net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and
+* u3  net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and
+* u4  net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and
+* u5  net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and
+* u6  net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and
+* u8  net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and
+* u9  net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and
+a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7
+a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11
+a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15
+a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19
+a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22
+a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3
+a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4
+a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5
+a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6
+a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8
+a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9
+a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10
+a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12
+a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 5e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4017/4017.pro b/src/SubcircuitLibrary/4017/4017.pro
new file mode 100644
index 00000000..8cdecd6c
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.pro
@@ -0,0 +1,72 @@
+update=Fri Jun 14 10:14:54 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=device
+LibName23=transistors
+LibName24=conn
+LibName25=linear
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_User
+LibName38=eSim_Plot
+
diff --git a/src/SubcircuitLibrary/4017/4017.sch b/src/SubcircuitLibrary/4017/4017.sch
new file mode 100644
index 00000000..05549a32
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.sch
@@ -0,0 +1,580 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:4017-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U7
+U 1 1 5C7B9B95
+P 2300 4100
+F 0 "U7" H 2300 4100 60  0000 C CNN
+F 1 "d_dff" H 2300 4250 60  0000 C CNN
+F 2 "" H 2300 4100 60  0000 C CNN
+F 3 "" H 2300 4100 60  0000 C CNN
+	1    2300 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U11
+U 1 1 5C7B9CEE
+P 3700 4100
+F 0 "U11" H 3700 4100 60  0000 C CNN
+F 1 "d_dff" H 3700 4250 60  0000 C CNN
+F 2 "" H 3700 4100 60  0000 C CNN
+F 3 "" H 3700 4100 60  0000 C CNN
+	1    3700 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U15
+U 1 1 5C7B9D3E
+P 5150 4100
+F 0 "U15" H 5150 4100 60  0000 C CNN
+F 1 "d_dff" H 5150 4250 60  0000 C CNN
+F 2 "" H 5150 4100 60  0000 C CNN
+F 3 "" H 5150 4100 60  0000 C CNN
+	1    5150 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U19
+U 1 1 5C7B9D85
+P 6550 4100
+F 0 "U19" H 6550 4100 60  0000 C CNN
+F 1 "d_dff" H 6550 4250 60  0000 C CNN
+F 2 "" H 6550 4100 60  0000 C CNN
+F 3 "" H 6550 4100 60  0000 C CNN
+	1    6550 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_dff U22
+U 1 1 5C7B9DD9
+P 8050 4100
+F 0 "U22" H 8050 4100 60  0000 C CNN
+F 1 "d_dff" H 8050 4250 60  0000 C CNN
+F 2 "" H 8050 4100 60  0000 C CNN
+F 3 "" H 8050 4100 60  0000 C CNN
+	1    8050 4100
+	1    0    0    -1  
+$EndComp
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+Connection ~ 2000 2450
+Wire Wire Line
+	8600 4400 8800 4400
+Wire Wire Line
+	8800 4400 8800 6350
+Wire Wire Line
+	8800 6350 1350 6350
+Wire Wire Line
+	1350 6350 1350 3600
+Wire Wire Line
+	1350 3600 1750 3600
+Connection ~ 1750 3600
+Wire Wire Line
+	2100 3300 3000 3300
+Wire Wire Line
+	3000 3300 3000 4400
+Connection ~ 2900 4400
+Connection ~ 2100 2500
+Connection ~ 2650 2700
+Wire Wire Line
+	2650 3250 2950 3250
+Wire Wire Line
+	2950 3250 2950 3750
+Connection ~ 2950 3750
+Wire Wire Line
+	4400 4400 4400 3200
+Wire Wire Line
+	4400 3200 2750 3200
+Connection ~ 2750 2550
+Wire Wire Line
+	3350 3250 4250 3250
+Wire Wire Line
+	4250 3250 4250 3750
+Connection ~ 3350 2750
+Wire Wire Line
+	3450 3150 5850 3150
+Wire Wire Line
+	5850 3150 5850 4400
+Connection ~ 5750 4400
+Connection ~ 3450 2600
+Wire Wire Line
+	3900 3100 5750 3100
+Wire Wire Line
+	5750 3100 5750 3750
+Connection ~ 5750 3750
+Connection ~ 3900 2800
+Wire Wire Line
+	4000 3050 7350 3050
+Wire Wire Line
+	7350 3050 7350 4400
+Wire Wire Line
+	7350 4400 7100 4400
+Connection ~ 4000 2650
+Wire Wire Line
+	4550 3000 7200 3000
+Wire Wire Line
+	7200 3000 7200 3750
+Connection ~ 7200 3750
+Connection ~ 4550 2850
+Wire Wire Line
+	5250 2950 8700 2950
+Wire Wire Line
+	8700 2950 8700 3750
+Wire Wire Line
+	8700 3750 8600 3750
+Connection ~ 5250 2900
+Wire Wire Line
+	2300 6700 1100 6700
+Connection ~ 2300 4900
+Wire Wire Line
+	1550 3350 1550 5150
+Wire Wire Line
+	1550 5150 2300 5150
+Connection ~ 2300 5150
+Connection ~ 2300 3350
+Wire Wire Line
+	2550 5350 2550 6650
+Wire Wire Line
+	2550 6650 2950 6650
+Wire Wire Line
+	2950 6650 2950 7200
+Wire Wire Line
+	2950 7200 2700 7200
+Connection ~ 2550 5350
+$Comp
+L PORT U1
+U 6 1 5C7C1634
+P 5300 1000
+F 0 "U1" H 5350 1100 30  0000 C CNN
+F 1 "PORT" H 5300 1000 30  0000 C CNN
+F 2 "" H 5300 1000 60  0000 C CNN
+F 3 "" H 5300 1000 60  0000 C CNN
+	6    5300 1000
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	5300 1250 5300 1400
+$Comp
+L PORT U1
+U 2 1 5C7BC7B8
+P 2700 1000
+F 0 "U1" H 2750 1100 30  0000 C CNN
+F 1 "PORT" H 2700 1000 30  0000 C CNN
+F 2 "" H 2700 1000 60  0000 C CNN
+F 3 "" H 2700 1000 60  0000 C CNN
+	2    2700 1000
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C7BC953
+P 2050 950
+F 0 "U1" H 2100 1050 30  0000 C CNN
+F 1 "PORT" H 2050 950 30  0000 C CNN
+F 2 "" H 2050 950 60  0000 C CNN
+F 3 "" H 2050 950 60  0000 C CNN
+	1    2050 950 
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C7BC9D8
+P 3400 950
+F 0 "U1" H 3450 1050 30  0000 C CNN
+F 1 "PORT" H 3400 950 30  0000 C CNN
+F 2 "" H 3400 950 60  0000 C CNN
+F 3 "" H 3400 950 60  0000 C CNN
+	3    3400 950 
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5C7BCAA7
+P 5850 950
+F 0 "U1" H 5900 1050 30  0000 C CNN
+F 1 "PORT" H 5850 950 30  0000 C CNN
+F 2 "" H 5850 950 60  0000 C CNN
+F 3 "" H 5850 950 60  0000 C CNN
+	7    5850 950 
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5C7BCB20
+P 6400 1000
+F 0 "U1" H 6450 1100 30  0000 C CNN
+F 1 "PORT" H 6400 1000 30  0000 C CNN
+F 2 "" H 6400 1000 60  0000 C CNN
+F 3 "" H 6400 1000 60  0000 C CNN
+	8    6400 1000
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C7BCBB1
+P 3950 950
+F 0 "U1" H 4000 1050 30  0000 C CNN
+F 1 "PORT" H 3950 950 30  0000 C CNN
+F 2 "" H 3950 950 60  0000 C CNN
+F 3 "" H 3950 950 60  0000 C CNN
+	4    3950 950 
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5C7BCF23
+P 7050 1000
+F 0 "U1" H 7100 1100 30  0000 C CNN
+F 1 "PORT" H 7050 1000 30  0000 C CNN
+F 2 "" H 7050 1000 60  0000 C CNN
+F 3 "" H 7050 1000 60  0000 C CNN
+	9    7050 1000
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C7BCFC0
+P 4600 950
+F 0 "U1" H 4650 1050 30  0000 C CNN
+F 1 "PORT" H 4600 950 30  0000 C CNN
+F 2 "" H 4600 950 60  0000 C CNN
+F 3 "" H 4600 950 60  0000 C CNN
+	5    4600 950 
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5C7BD0A5
+P 7750 1000
+F 0 "U1" H 7800 1100 30  0000 C CNN
+F 1 "PORT" H 7750 1000 30  0000 C CNN
+F 2 "" H 7750 1000 60  0000 C CNN
+F 3 "" H 7750 1000 60  0000 C CNN
+	10   7750 1000
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5C7BD5BB
+P 850 6700
+F 0 "U1" H 900 6800 30  0000 C CNN
+F 1 "PORT" H 850 6700 30  0000 C CNN
+F 2 "" H 850 6700 60  0000 C CNN
+F 3 "" H 850 6700 60  0000 C CNN
+	11   850  6700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2050 1200 2050 1400
+Wire Wire Line
+	2700 1250 2700 1400
+Wire Wire Line
+	3400 1200 3400 1400
+Wire Wire Line
+	3950 1200 3950 1400
+Wire Wire Line
+	4600 1200 4600 1400
+Wire Wire Line
+	5850 1200 5850 1400
+Wire Wire Line
+	6400 1250 6400 1400
+Wire Wire Line
+	7050 1250 7050 1400
+Wire Wire Line
+	7750 1250 7750 1400
+$Comp
+L PORT U1
+U 12 1 5C8A0119
+P 2450 7200
+F 0 "U1" H 2500 7300 30  0000 C CNN
+F 1 "PORT" H 2450 7200 30  0000 C CNN
+F 2 "" H 2450 7200 60  0000 C CNN
+F 3 "" H 2450 7200 60  0000 C CNN
+	12   2450 7200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C89F7BC
+P 2100 1850
+F 0 "U2" H 2100 1850 60  0000 C CNN
+F 1 "d_and" H 2150 1950 60  0000 C CNN
+F 2 "" H 2100 1850 60  0000 C CNN
+F 3 "" H 2100 1850 60  0000 C CNN
+	1    2100 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C89FA46
+P 2750 1850
+F 0 "U3" H 2750 1850 60  0000 C CNN
+F 1 "d_and" H 2800 1950 60  0000 C CNN
+F 2 "" H 2750 1850 60  0000 C CNN
+F 3 "" H 2750 1850 60  0000 C CNN
+	1    2750 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U4
+U 1 1 5C89FAD5
+P 3450 1850
+F 0 "U4" H 3450 1850 60  0000 C CNN
+F 1 "d_and" H 3500 1950 60  0000 C CNN
+F 2 "" H 3450 1850 60  0000 C CNN
+F 3 "" H 3450 1850 60  0000 C CNN
+	1    3450 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U5
+U 1 1 5C89FB62
+P 4000 1850
+F 0 "U5" H 4000 1850 60  0000 C CNN
+F 1 "d_and" H 4050 1950 60  0000 C CNN
+F 2 "" H 4000 1850 60  0000 C CNN
+F 3 "" H 4000 1850 60  0000 C CNN
+	1    4000 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U6
+U 1 1 5C89FEBF
+P 4650 1850
+F 0 "U6" H 4650 1850 60  0000 C CNN
+F 1 "d_and" H 4700 1950 60  0000 C CNN
+F 2 "" H 4650 1850 60  0000 C CNN
+F 3 "" H 4650 1850 60  0000 C CNN
+	1    4650 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U8
+U 1 1 5C89FF2C
+P 5350 1850
+F 0 "U8" H 5350 1850 60  0000 C CNN
+F 1 "d_and" H 5400 1950 60  0000 C CNN
+F 2 "" H 5350 1850 60  0000 C CNN
+F 3 "" H 5350 1850 60  0000 C CNN
+	1    5350 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U9
+U 1 1 5C89FF96
+P 5900 1850
+F 0 "U9" H 5900 1850 60  0000 C CNN
+F 1 "d_and" H 5950 1950 60  0000 C CNN
+F 2 "" H 5900 1850 60  0000 C CNN
+F 3 "" H 5900 1850 60  0000 C CNN
+	1    5900 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U10
+U 1 1 5C8A066D
+P 6450 1850
+F 0 "U10" H 6450 1850 60  0000 C CNN
+F 1 "d_and" H 6500 1950 60  0000 C CNN
+F 2 "" H 6450 1850 60  0000 C CNN
+F 3 "" H 6450 1850 60  0000 C CNN
+	1    6450 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U12
+U 1 1 5C8A06D8
+P 7100 1850
+F 0 "U12" H 7100 1850 60  0000 C CNN
+F 1 "d_and" H 7150 1950 60  0000 C CNN
+F 2 "" H 7100 1850 60  0000 C CNN
+F 3 "" H 7100 1850 60  0000 C CNN
+	1    7100 1850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L d_and U13
+U 1 1 5C8A12F5
+P 7800 1850
+F 0 "U13" H 7800 1850 60  0000 C CNN
+F 1 "d_and" H 7850 1950 60  0000 C CNN
+F 2 "" H 7800 1850 60  0000 C CNN
+F 3 "" H 7800 1850 60  0000 C CNN
+	1    7800 1850
+	0    -1   -1   0   
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4017/4017.sub b/src/SubcircuitLibrary/4017/4017.sub
new file mode 100644
index 00000000..2e27ab61
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.sub
@@ -0,0 +1,66 @@
+* Subcircuit 4017
+.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir
+* u7  net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff
+* u11  net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff
+* u15  net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff
+* u19  net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff
+* u22  net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and
+* u3  net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and
+* u4  net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and
+* u5  net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and
+* u6  net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and
+* u8  net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and
+* u9  net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and
+a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7
+a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11
+a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15
+a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19
+a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22
+a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3
+a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4
+a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5
+a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6
+a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8
+a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9
+a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10
+a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12
+a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4017
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml
new file mode 100644
index 00000000..9dfd97a3
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/D.lib b/src/SubcircuitLibrary/4017/D.lib
new file mode 100644
index 00000000..adbdfb35
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/D.lib
@@ -0,0 +1,11 @@
+.MODEL 1N4148 D(
++  Vj=1
++  Cjo=1.700E-12
++  Rs=4.755E-01
++  Is=2.495E-09
++  M=1.959E-01
++  N=1.679E+00
++  Bv=1.000E+02
++  tt=3.030E-09
++  Ibv=1.000E-04
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/analysis b/src/SubcircuitLibrary/4017/analysis
new file mode 100644
index 00000000..40bd9d97
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/analysis
@@ -0,0 +1 @@
+.tran 5e-03 100e-03 0e-00
\ No newline at end of file