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| author | rahulp13 | 2020-02-21 12:36:46 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-21 12:36:46 +0530 |
| commit | 47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch) | |
| tree | 55aefefe974f151de76c6a2dbe8df3b4c3393bbe /src/SubcircuitLibrary/2bitmul/half_adder.sub | |
| parent | 453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff) | |
| download | eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2 eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip | |
restructured eSim libraries
Diffstat (limited to 'src/SubcircuitLibrary/2bitmul/half_adder.sub')
| -rw-r--r-- | src/SubcircuitLibrary/2bitmul/half_adder.sub | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sub b/src/SubcircuitLibrary/2bitmul/half_adder.sub deleted file mode 100644 index e9f92223..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit half_adder -.subckt half_adder 1 4 3 2 -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends half_adder
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