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authorrahulp132020-02-21 12:36:46 +0530
committerrahulp132020-02-21 12:36:46 +0530
commit47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch)
tree55aefefe974f151de76c6a2dbe8df3b4c3393bbe /src/SubcircuitLibrary/2bitmul/half_adder.cir
parent453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff)
downloadeSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz
eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2
eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip
restructured eSim libraries
Diffstat (limited to 'src/SubcircuitLibrary/2bitmul/half_adder.cir')
-rw-r--r--src/SubcircuitLibrary/2bitmul/half_adder.cir11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir b/src/SubcircuitLibrary/2bitmul/half_adder.cir
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-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U2 1 4 3 d_xor
-U3 1 4 2 d_and
-U1 1 4 3 2 PORT
-
-.end