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| author | Rahul P | 2020-03-04 17:01:11 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-04 17:01:11 +0530 |
| commit | 8ffe81b36caa259151978de0434e4e0c5c32d217 (patch) | |
| tree | 32202454d13dfabbf6556e98987f2a9632619ea9 /src/SubcircuitLibrary/2bitmul/half_adder.cir | |
| parent | e40317e709c220176fc5b7edf23d4434504335b0 (diff) | |
| parent | 13f3bcfda9416624cebbf5705de398e8efcad344 (diff) | |
| download | eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2 eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.zip | |
Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'src/SubcircuitLibrary/2bitmul/half_adder.cir')
| -rw-r--r-- | src/SubcircuitLibrary/2bitmul/half_adder.cir | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir b/src/SubcircuitLibrary/2bitmul/half_adder.cir deleted file mode 100644 index 8b2e7e06..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder.cir +++ /dev/null @@ -1,11 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 1 4 3 d_xor -U3 1 4 2 d_and -U1 1 4 3 2 PORT - -.end |