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| author | rahulp13 | 2020-02-21 12:36:46 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-21 12:36:46 +0530 |
| commit | 47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch) | |
| tree | 55aefefe974f151de76c6a2dbe8df3b4c3393bbe /src/SubcircuitLibrary/2bitmul/2bitmul.cir.out | |
| parent | 453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff) | |
| download | eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2 eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip | |
restructured eSim libraries
Diffstat (limited to 'src/SubcircuitLibrary/2bitmul/2bitmul.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/2bitmul/2bitmul.cir.out | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out deleted file mode 100644 index 71766bd8..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out +++ /dev/null @@ -1,31 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir - -.include half_adder.sub -* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and -* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and -* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and -* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and -x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder -x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port -a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 -a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 -a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end |