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| author | saurabhb17 | 2019-07-02 17:08:16 +0530 |
|---|---|---|
| committer | GitHub | 2019-07-02 17:08:16 +0530 |
| commit | 83d93769478a1805083666479d4ff83b875ba955 (patch) | |
| tree | d97a2f3543ab4e5164490495ee19f20352ecb71f /src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out | |
| parent | 29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (diff) | |
| parent | 8c44f97b533607d057a28e029e42f001270f4fd4 (diff) | |
| download | eSim-83d93769478a1805083666479d4ff83b875ba955.tar.gz eSim-83d93769478a1805083666479d4ff83b875ba955.tar.bz2 eSim-83d93769478a1805083666479d4ff83b875ba955.zip | |
Merge pull request #115 from nilshah98/ese
Adding the work done by FSF 2019 eSim ECE Fellows
Diffstat (limited to 'src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out new file mode 100644 index 00000000..4232f26a --- /dev/null +++ b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out @@ -0,0 +1,20 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/2bit_upcounter/2bit_upcounter.cir + +* u2 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ d_dff +* u3 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ u2 +a2 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ u3 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |