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author | fossee | 2019-08-29 12:03:11 +0530 |
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committer | fossee | 2019-08-29 12:03:11 +0530 |
commit | fe3bd934634bb2dae1cadf35e7c6d59facbedf66 (patch) | |
tree | ab841ad9ca3d56f7eb85cb3650f6608b80656027 /nghdl/Example/xor/myxor.vhdl | |
parent | f7567ac99f21fb6c87d60f309f0aa71dee6ae975 (diff) | |
download | eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.tar.gz eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.tar.bz2 eSim-fe3bd934634bb2dae1cadf35e7c6d59facbedf66.zip |
adding files
Diffstat (limited to 'nghdl/Example/xor/myxor.vhdl')
-rw-r--r-- | nghdl/Example/xor/myxor.vhdl | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/nghdl/Example/xor/myxor.vhdl b/nghdl/Example/xor/myxor.vhdl new file mode 100644 index 00000000..b49f3cad --- /dev/null +++ b/nghdl/Example/xor/myxor.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity myxor is + port (a : in std_logic_vector(0 downto 0); + b : in std_logic_vector(0 downto 0); + c : out std_logic_vector(0 downto 0)); + end myxor; + + architecture rtl of myxor is + begin + + c <= a xor b; + + end rtl; |