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authorrahulp132020-03-02 16:19:12 +0530
committerrahulp132020-03-02 16:19:12 +0530
commit55b7386f67afe1429f61ef9b8f923437419c7b1e (patch)
tree7fe7ad86944de9820668a19d4cf0ebd212147f6c /library/kicadLibrary/template/raspberrypi-gpio
parent977bfed94cb0e5e4efc6b68a143d8b79682209c2 (diff)
downloadeSim-55b7386f67afe1429f61ef9b8f923437419c7b1e.tar.gz
eSim-55b7386f67afe1429f61ef9b8f923437419c7b1e.tar.bz2
eSim-55b7386f67afe1429f61ef9b8f923437419c7b1e.zip
update libraries
Diffstat (limited to 'library/kicadLibrary/template/raspberrypi-gpio')
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/meta/brd.pngbin0 -> 57538 bytes
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/meta/icon.pngbin0 -> 5374 bytes
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/meta/info.html25
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio-cache.lib86
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb320
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.pro106
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.sch168
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.stf1
8 files changed, 706 insertions, 0 deletions
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/meta/brd.png b/library/kicadLibrary/template/raspberrypi-gpio/meta/brd.png
new file mode 100644
index 00000000..55e41753
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/meta/brd.png
Binary files differ
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/meta/icon.png b/library/kicadLibrary/template/raspberrypi-gpio/meta/icon.png
new file mode 100644
index 00000000..a8d473b6
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/meta/icon.png
Binary files differ
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/meta/info.html b/library/kicadLibrary/template/raspberrypi-gpio/meta/info.html
new file mode 100644
index 00000000..f641c66c
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/meta/info.html
@@ -0,0 +1,25 @@
+<html>
+<head>
+<title>Raspberry Pi - Expansion Board</title>
+</head>
+<body>
+<h1>Raspberry Pi</h1>
+<h2>Expansion Board</h2>
+
+<p>This project template is the basis of an expansion board for the
+<a href="http://www.raspberrypi.org/" target="blank">Raspberry Pi $25 ARM
+board.</a></p>
+
+<p>This base project includes a PCB edge defined as the same size as the
+Raspberry-Pi PCB with the connectors placed correctly to align the two boards.
+All IO present on the Raspberry-Pi board is connected to the project through the
+0.1" expansion headers.</p>
+
+<p>The board outline looks like the following:</p>
+
+<p><img src="brd.png"></p>
+
+<p>(c)2012 Brian Sidebotham<br>
+(c)2012 Kicad Developers<br></p>
+</body>
+</html>
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio-cache.lib b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio-cache.lib
new file mode 100644
index 00000000..0a3d6ecc
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio-cache.lib
@@ -0,0 +1,86 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# +3V3
+#
+DEF +3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# +5V
+#
+DEF +5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+5V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +5V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# CONN_13X2
+#
+DEF CONN_13X2 P 0 10 Y N 1 F N
+F0 "P" 0 700 60 H V C CNN
+F1 "CONN_13X2" 0 0 50 V V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -100 650 100 -650 0 1 0 N
+X P1 1 -400 600 300 R 40 30 1 1 P I
+X P2 2 400 600 300 L 40 30 1 1 P I
+X P3 3 -400 500 300 R 40 30 1 1 P I
+X P4 4 400 500 300 L 40 30 1 1 P I
+X P5 5 -400 400 300 R 40 30 1 1 P I
+X P6 6 400 400 300 L 40 30 1 1 P I
+X P7 7 -400 300 300 R 40 30 1 1 P I
+X P8 8 400 300 300 L 40 30 1 1 P I
+X P9 9 -400 200 300 R 40 30 1 1 P I
+X P10 10 400 200 300 L 40 30 1 1 P I
+X P20 20 400 -300 300 L 40 30 1 1 P I
+X P11 11 -400 100 300 R 40 30 1 1 P I
+X P21 21 -400 -400 300 R 40 30 1 1 P I
+X P12 12 400 100 300 L 40 30 1 1 P I
+X P22 22 400 -400 300 L 40 30 1 1 P I
+X P13 13 -400 0 300 R 40 30 1 1 P I
+X P23 23 -400 -500 300 R 40 30 1 1 P I
+X P14 14 400 0 300 L 40 30 1 1 P I
+X P20 24 400 -500 300 L 40 30 1 1 P I
+X P15 15 -400 -100 300 R 40 30 1 1 P I
+X P24 25 -400 -600 300 R 40 30 1 1 P I
+X P16 16 400 -100 300 L 40 30 1 1 P I
+X P22 26 400 -600 300 L 40 30 1 1 P I
+X P17 17 -400 -200 300 R 40 30 1 1 P I
+X P18 18 400 -200 300 L 40 30 1 1 P I
+X P19 19 -400 -300 300 R 40 30 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb
new file mode 100644
index 00000000..d6ce37a3
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb
@@ -0,0 +1,320 @@
+(kicad_pcb (version 4) (host pcbnew 4.0.5)
+
+ (general
+ (links 0)
+ (no_connects 0)
+ (area 143.424999 124.924999 228.575001 181.075001)
+ (thickness 1.6)
+ (drawings 41)
+ (tracks 0)
+ (zones 0)
+ (modules 1)
+ (nets 27)
+ )
+
+ (page A3)
+ (title_block
+ (date "15 nov 2012")
+ )
+
+ (layers
+ (0 F.Cu signal)
+ (31 B.Cu signal)
+ (32 B.Adhes user)
+ (33 F.Adhes user)
+ (34 B.Paste user)
+ (35 F.Paste user)
+ (36 B.SilkS user)
+ (37 F.SilkS user)
+ (38 B.Mask user)
+ (39 F.Mask user)
+ (40 Dwgs.User user)
+ (41 Cmts.User user)
+ (42 Eco1.User user)
+ (43 Eco2.User user)
+ (44 Edge.Cuts user)
+ )
+
+ (setup
+ (last_trace_width 0.2)
+ (trace_clearance 0.2)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.1524)
+ (segment_width 0.2)
+ (edge_width 0.15)
+ (via_size 0.9)
+ (via_drill 0.6)
+ (via_min_size 0.8)
+ (via_min_drill 0.5)
+ (uvia_size 0.5)
+ (uvia_drill 0.1)
+ (uvias_allowed no)
+ (uvia_min_size 0.5)
+ (uvia_min_drill 0.1)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1 1)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1 1)
+ (pad_drill 0.6)
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 143.5 181)
+ (visible_elements 7FFFFFFF)
+ (pcbplotparams
+ (layerselection 0x00030_80000001)
+ (usegerberextensions true)
+ (excludeedgelayer true)
+ (linewidth 0.150000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (hpglpenoverlay 2)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 1)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 +5V)
+ (net 2 GND)
+ (net 3 +3V3)
+ (net 4 "/GPIO0(SDA)")
+ (net 5 "Net-(P1-Pad4)")
+ (net 6 "/GPIO1(SCL)")
+ (net 7 /GPIO4)
+ (net 8 /TXD)
+ (net 9 "Net-(P1-Pad9)")
+ (net 10 /RXD)
+ (net 11 /GPIO17)
+ (net 12 /GPIO18)
+ (net 13 /GPIO21)
+ (net 14 "Net-(P1-Pad14)")
+ (net 15 /GPIO22)
+ (net 16 /GPIO23)
+ (net 17 "Net-(P1-Pad17)")
+ (net 18 /GPIO24)
+ (net 19 "/GPIO10(MOSI)")
+ (net 20 "Net-(P1-Pad20)")
+ (net 21 "/GPIO9(MISO)")
+ (net 22 /GPIO25)
+ (net 23 "/GPIO11(SCLK)")
+ (net 24 "/GPIO8(CE0)")
+ (net 25 "Net-(P1-Pad25)")
+ (net 26 "/GPIO7(CE1)")
+
+ (net_class Default "This is the default net class."
+ (clearance 0.2)
+ (trace_width 0.2)
+ (via_dia 0.9)
+ (via_drill 0.6)
+ (uvia_dia 0.5)
+ (uvia_drill 0.1)
+ (add_net +3V3)
+ (add_net +5V)
+ (add_net "/GPIO0(SDA)")
+ (add_net "/GPIO1(SCL)")
+ (add_net "/GPIO10(MOSI)")
+ (add_net "/GPIO11(SCLK)")
+ (add_net /GPIO17)
+ (add_net /GPIO18)
+ (add_net /GPIO21)
+ (add_net /GPIO22)
+ (add_net /GPIO23)
+ (add_net /GPIO24)
+ (add_net /GPIO25)
+ (add_net /GPIO4)
+ (add_net "/GPIO7(CE1)")
+ (add_net "/GPIO8(CE0)")
+ (add_net "/GPIO9(MISO)")
+ (add_net /RXD)
+ (add_net /TXD)
+ (add_net GND)
+ (add_net "Net-(P1-Pad14)")
+ (add_net "Net-(P1-Pad17)")
+ (add_net "Net-(P1-Pad20)")
+ (add_net "Net-(P1-Pad25)")
+ (add_net "Net-(P1-Pad4)")
+ (add_net "Net-(P1-Pad9)")
+ )
+
+ (net_class Power ""
+ (clearance 0.2)
+ (trace_width 0.5)
+ (via_dia 1)
+ (via_drill 0.7)
+ (uvia_dia 0.5)
+ (uvia_drill 0.1)
+ )
+
+ (module Pin_Headers:Pin_Header_Straight_2x13 locked (layer F.Cu) (tedit 584FB37B) (tstamp 584FB325)
+ (at 145.75536 130.27914 90)
+ (descr "Through hole pin header")
+ (tags "pin header")
+ (path /50A55ABA)
+ (fp_text reference P1 (at 1.5875 32.6136 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value CONN_13X2 (at -2.37998 16.29664 180) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -1.75 -1.75) (end -1.75 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 4.3 -1.75) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.75 32.25) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 3.81 -1.27) (end 3.81 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.27 1.27) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start 3.81 31.75) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
+ (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15))
+ (pad 1 thru_hole rect (at 0 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 3 +3V3))
+ (pad 2 thru_hole oval (at 2.54 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 1 +5V))
+ (pad 3 thru_hole oval (at 0 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 4 "/GPIO0(SDA)"))
+ (pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 5 "Net-(P1-Pad4)"))
+ (pad 5 thru_hole oval (at 0 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 6 "/GPIO1(SCL)"))
+ (pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 2 GND))
+ (pad 7 thru_hole oval (at 0 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 7 /GPIO4))
+ (pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 8 /TXD))
+ (pad 9 thru_hole oval (at 0 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 9 "Net-(P1-Pad9)"))
+ (pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 10 /RXD))
+ (pad 11 thru_hole oval (at 0 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 11 /GPIO17))
+ (pad 12 thru_hole oval (at 2.54 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 12 /GPIO18))
+ (pad 13 thru_hole oval (at 0 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 13 /GPIO21))
+ (pad 14 thru_hole oval (at 2.54 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 14 "Net-(P1-Pad14)"))
+ (pad 15 thru_hole oval (at 0 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 15 /GPIO22))
+ (pad 16 thru_hole oval (at 2.54 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 16 /GPIO23))
+ (pad 17 thru_hole oval (at 0 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 17 "Net-(P1-Pad17)"))
+ (pad 18 thru_hole oval (at 2.54 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 18 /GPIO24))
+ (pad 19 thru_hole oval (at 0 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 19 "/GPIO10(MOSI)"))
+ (pad 20 thru_hole oval (at 2.54 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 20 "Net-(P1-Pad20)"))
+ (pad 21 thru_hole oval (at 0 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 21 "/GPIO9(MISO)"))
+ (pad 22 thru_hole oval (at 2.54 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 22 /GPIO25))
+ (pad 23 thru_hole oval (at 0 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 23 "/GPIO11(SCLK)"))
+ (pad 24 thru_hole oval (at 2.54 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 24 "/GPIO8(CE0)"))
+ (pad 25 thru_hole oval (at 0 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 25 "Net-(P1-Pad25)"))
+ (pad 26 thru_hole oval (at 2.54 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 26 "/GPIO7(CE1)"))
+ (model Pin_Headers.3dshapes/Pin_Header_Straight_2x13.wrl
+ (at (xyz 0.05 -0.6 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 90))
+ )
+ )
+
+ (gr_text "RASPBERRY-PI ADDON BOARD\nVIEW FROM TOP\nNOTE: P1 SHOULD BE FITTED ON THE REVERSE OF THE BOARD" (at 144 183.5) (layer Dwgs.User)
+ (effects (font (size 2 1.7) (thickness 0.12)) (justify left))
+ )
+ (dimension 56 (width 0.12) (layer Dwgs.User)
+ (gr_text "56.000 mm" (at 132 153 90) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (feature1 (pts (xy 143.5 125) (xy 131 125)))
+ (feature2 (pts (xy 143.5 181) (xy 131 181)))
+ (crossbar (pts (xy 133 181) (xy 133 125)))
+ (arrow1a (pts (xy 133 125) (xy 133.58642 126.126503)))
+ (arrow1b (pts (xy 133 125) (xy 132.41358 126.126503)))
+ (arrow2a (pts (xy 133 181) (xy 133.58642 179.873497)))
+ (arrow2b (pts (xy 133 181) (xy 132.41358 179.873497)))
+ )
+ (dimension 85 (width 0.12) (layer Dwgs.User)
+ (gr_text "85.000 mm" (at 186 113.000001) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (feature1 (pts (xy 228.5 125) (xy 228.5 112.000001)))
+ (feature2 (pts (xy 143.5 125) (xy 143.5 112.000001)))
+ (crossbar (pts (xy 143.5 114.000001) (xy 228.5 114.000001)))
+ (arrow1a (pts (xy 228.5 114.000001) (xy 227.373497 114.586421)))
+ (arrow1b (pts (xy 228.5 114.000001) (xy 227.373497 113.413581)))
+ (arrow2a (pts (xy 143.5 114.000001) (xy 144.626503 114.586421)))
+ (arrow2b (pts (xy 143.5 114.000001) (xy 144.626503 113.413581)))
+ )
+ (gr_text "RCA\nREMOVE WITH\nSTD HEADERS\n!NO TH ABOVE!" (at 188.5 118) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_text "1/8\" JACK\nOK WITH STD\nHEADERS\n!NO TH ABOVE!" (at 207.5 118) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_line (start 228.5 142) (end 228.5 125) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 217.5 142) (end 228.5 142) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 217.5 157) (end 217.5 142) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 228.5 157) (end 217.5 157) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 228.5 181) (end 228.5 157) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_text "DOUBLE USB\nCUTOUT FOR ALL\nBOARDS" (at 236.5 149) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_text "RJ45\nCUTOUT FOR STD\nHEADERS\n!NO TH ABOVE!" (at 236.5 170) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_line (start 207.5 181) (end 228.5 162) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 207.5 162) (end 228.5 181) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 207.5 162) (end 228.5 162) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 207.5 181) (end 207.5 162) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 228.5 181) (end 207.5 181) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 228.5 162) (end 228.5 181) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 217.5 157) (end 228.5 142) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 217.5 142) (end 228.5 157) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 217.5 142) (end 228.5 142) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 217.5 157) (end 217.5 142) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 228.5 157) (end 217.5 157) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 228.5 142) (end 228.5 157) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 182.5 125) (end 194.5 139) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 182.5 139) (end 194.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 194.5 139) (end 194.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 182.5 139) (end 194.5 139) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 182.5 138) (end 182.5 139) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 214.5 125) (end 200.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 200.5 125) (end 214.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 200.5 138) (end 200.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 214.5 138) (end 200.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 214.5 125) (end 214.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 200.5 125) (end 214.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 194.5 125) (end 182.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 194.5 138) (end 194.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 182.5 125) (end 182.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 228.5 125) (end 143.5 125) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 143.5 181) (end 228.5 181) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 143.5 125) (end 143.5 181) (angle 90) (layer Edge.Cuts) (width 0.15))
+
+)
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.pro b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.pro
new file mode 100644
index 00000000..575fe0dc
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.pro
@@ -0,0 +1,106 @@
+update=13/12/2016 09:33:12
+version=1
+last_client=kicad
+[cvpcb]
+version=1
+NetITyp=0
+NetIExt=.net
+PkgIExt=.pkg
+NetDir=
+LibDir=
+NetType=0
+[cvpcb/libraries]
+EquName1=devcms
+[pcbnew]
+version=1
+PadDrlX=320
+PadDimH=600
+PadDimV=600
+PadForm=1
+PadMask=14745599
+ViaDiam=450
+ViaDril=250
+Isol=60
+Countlayer=2
+Lpiste=170
+RouteTo=15
+RouteBo=0
+TypeVia=3
+Segm45=1
+Racc45=1
+Unite=0
+SegFill=1
+SegAffG=0
+NewAffG=1
+PadFill=1
+PadAffG=1
+PadSNum=1
+ModAffC=0
+ModAffT=0
+PcbAffT=0
+SgPcb45=1
+TxtPcbV=800
+TxtPcbH=600
+TxtModV=600
+TxtModH=600
+TxtModW=120
+HPGLnum=1
+HPGdiam=15
+HPGLSpd=20
+HPGLrec=2
+HPGLorg=0
+GERBmin=15
+VEgarde=100
+DrawLar=150
+EdgeLar=150
+TxtLar=120
+MSegLar=150
+ForPlot=1
+WpenSer=10
+UserGrX=0,01
+UserGrY=0,01
+UserGrU=1
+DivGrPc=1
+TimeOut=600
+MaxLnkS=3
+ShowRat=0
+ShowMRa=1
+[pcbnew/libraries]
+LibDir=
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=libcms
+LibName7=display
+LibName8=valves
+LibName9=led
+LibName10=dip_sockets
+[general]
+version=1
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=microcontrollers
+LibName13=dsp
+LibName14=microchip
+LibName15=analog_switches
+LibName16=motorola
+LibName17=texas
+LibName18=intel
+LibName19=audio
+LibName20=interface
+LibName21=opto
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.sch b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.sch
new file mode 100644
index 00000000..5ec292d2
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.sch
@@ -0,0 +1,168 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:opto
+LIBS:raspberrypi-gpio-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "15 nov 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CONN_13X2 P1
+U 1 1 50A55ABA
+P 2400 1800
+F 0 "P1" H 2400 2500 60 0000 C CNN
+F 1 "CONN_13X2" V 2400 1800 50 0000 C CNN
+F 2 "Pin_Headers:Pin_Header_Straight_2x13" H 2400 1100 30 0000 C CNN
+F 3 "" H 2400 1800 60 0001 C CNN
+ 1 2400 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L +3.3V #PWR01
+U 1 1 50A55B18
+P 1900 1050
+F 0 "#PWR01" H 1900 900 50 0001 C CNN
+F 1 "+3.3V" H 1900 1190 50 0000 C CNN
+F 2 "" H 1900 1050 50 0000 C CNN
+F 3 "" H 1900 1050 50 0000 C CNN
+ 1 1900 1050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1900 1050 1900 1200
+Wire Wire Line
+ 1900 1200 2000 1200
+$Comp
+L +5V #PWR02
+U 1 1 50A55B2E
+P 2900 1050
+F 0 "#PWR02" H 2900 900 50 0001 C CNN
+F 1 "+5V" H 2900 1190 50 0000 C CNN
+F 2 "" H 2900 1050 50 0000 C CNN
+F 3 "" H 2900 1050 50 0000 C CNN
+ 1 2900 1050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2900 1050 2900 1200
+Wire Wire Line
+ 2900 1200 2800 1200
+NoConn ~ 2800 1300
+Wire Wire Line
+ 2000 1300 1250 1300
+Wire Wire Line
+ 2000 1400 1250 1400
+Text Label 1250 1300 0 60 ~ 0
+GPIO0(SDA)
+Text Label 1250 1400 0 60 ~ 0
+GPIO1(SCL)
+Wire Wire Line
+ 2000 1500 1250 1500
+Text Label 1250 1500 0 60 ~ 0
+GPIO4
+NoConn ~ 2000 1600
+Wire Wire Line
+ 2000 1700 1250 1700
+Wire Wire Line
+ 2000 1800 1250 1800
+Wire Wire Line
+ 2000 1900 1250 1900
+Text Label 1250 1700 0 60 ~ 0
+GPIO17
+Text Label 1250 1800 0 60 ~ 0
+GPIO21
+Text Label 1250 1900 0 60 ~ 0
+GPIO22
+NoConn ~ 2000 2000
+Wire Wire Line
+ 2000 2100 1250 2100
+Wire Wire Line
+ 2000 2200 1250 2200
+Wire Wire Line
+ 2000 2300 1250 2300
+Text Label 1250 2100 0 60 ~ 0
+GPIO10(MOSI)
+Text Label 1250 2200 0 60 ~ 0
+GPIO9(MISO)
+Text Label 1250 2300 0 60 ~ 0
+GPIO11(SCLK)
+NoConn ~ 2000 2400
+$Comp
+L GND #PWR03
+U 1 1 50A55C3F
+P 2900 2500
+F 0 "#PWR03" H 2900 2250 50 0001 C CNN
+F 1 "GND" H 2900 2350 50 0000 C CNN
+F 2 "" H 2900 2500 50 0000 C CNN
+F 3 "" H 2900 2500 50 0000 C CNN
+ 1 2900 2500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2900 2500 2900 1400
+Wire Wire Line
+ 2900 1400 2800 1400
+Wire Wire Line
+ 2800 1500 3500 1500
+Wire Wire Line
+ 2800 1600 3500 1600
+Text Label 3500 1500 2 60 ~ 0
+TXD
+Text Label 3500 1600 2 60 ~ 0
+RXD
+Wire Wire Line
+ 2800 1700 3500 1700
+Text Label 3500 1700 2 60 ~ 0
+GPIO18
+NoConn ~ 2800 1800
+Wire Wire Line
+ 2800 1900 3500 1900
+Wire Wire Line
+ 2800 2000 3500 2000
+Text Label 3500 1900 2 60 ~ 0
+GPIO23
+Text Label 3500 2000 2 60 ~ 0
+GPIO24
+NoConn ~ 2800 2100
+Wire Wire Line
+ 2800 2200 3500 2200
+Text Label 3500 2200 2 60 ~ 0
+GPIO25
+Wire Wire Line
+ 2800 2300 3500 2300
+Wire Wire Line
+ 2800 2400 3500 2400
+Text Label 3500 2300 2 60 ~ 0
+GPIO8(CE0)
+Text Label 3500 2400 2 60 ~ 0
+GPIO7(CE1)
+$EndSCHEMATC
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.stf b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.stf
new file mode 100644
index 00000000..d9a206f0
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.stf
@@ -0,0 +1 @@
+comp = "P1" module = "HE10_26D"
generated by cgit (git 2.34.1) at 2024-12-22 19:50:25 +0000