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authorRahul P2020-03-04 17:01:11 +0530
committerGitHub2020-03-04 17:01:11 +0530
commit8ffe81b36caa259151978de0434e4e0c5c32d217 (patch)
tree32202454d13dfabbf6556e98987f2a9632619ea9 /library/kicadLibrary/template/EuroCard160mmX100mm/EuroCard160mmX100mm.kicad_pcb
parente40317e709c220176fc5b7edf23d4434504335b0 (diff)
parent13f3bcfda9416624cebbf5705de398e8efcad344 (diff)
downloadeSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz
eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2
eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.zip
Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'library/kicadLibrary/template/EuroCard160mmX100mm/EuroCard160mmX100mm.kicad_pcb')
-rw-r--r--library/kicadLibrary/template/EuroCard160mmX100mm/EuroCard160mmX100mm.kicad_pcb106
1 files changed, 106 insertions, 0 deletions
diff --git a/library/kicadLibrary/template/EuroCard160mmX100mm/EuroCard160mmX100mm.kicad_pcb b/library/kicadLibrary/template/EuroCard160mmX100mm/EuroCard160mmX100mm.kicad_pcb
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--- /dev/null
+++ b/library/kicadLibrary/template/EuroCard160mmX100mm/EuroCard160mmX100mm.kicad_pcb
@@ -0,0 +1,106 @@
+(kicad_pcb (version 20170123) (host pcbnew "(2017-07-16 revision e797af331)-master")
+
+ (general
+ (thickness 1.6)
+ (drawings 4)
+ (tracks 0)
+ (zones 0)
+ (modules 0)
+ (nets 1)
+ )
+
+ (page A4)
+ (layers
+ (0 F.Cu signal)
+ (31 B.Cu signal)
+ (32 B.Adhes user)
+ (33 F.Adhes user)
+ (34 B.Paste user)
+ (35 F.Paste user)
+ (36 B.SilkS user)
+ (37 F.SilkS user)
+ (38 B.Mask user)
+ (39 F.Mask user)
+ (40 Dwgs.User user)
+ (41 Cmts.User user)
+ (42 Eco1.User user)
+ (43 Eco2.User user)
+ (44 Edge.Cuts user)
+ (45 Margin user)
+ (46 B.CrtYd user)
+ (47 F.CrtYd user)
+ (48 B.Fab user)
+ (49 F.Fab user)
+ )
+
+ (setup
+ (last_trace_width 0.25)
+ (trace_clearance 0.2)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.2)
+ (segment_width 0.2)
+ (edge_width 0.15)
+ (via_size 0.8)
+ (via_drill 0.4)
+ (via_min_size 0.4)
+ (via_min_drill 0.3)
+ (uvia_size 0.3)
+ (uvia_drill 0.1)
+ (uvias_allowed no)
+ (uvia_min_size 0.2)
+ (uvia_min_drill 0.1)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1.524 1.524)
+ (pad_drill 0.762)
+ (pad_to_mask_clearance 0.2)
+ (aux_axis_origin 0 0)
+ (grid_origin 55 145)
+ (visible_elements FFFFFF7F)
+ (pcbplotparams
+ (layerselection 0x00030_ffffffff)
+ (usegerberextensions false)
+ (excludeedgelayer true)
+ (linewidth 0.100000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+
+ (net_class Default "This is the default net class."
+ (clearance 0.2)
+ (trace_width 0.25)
+ (via_dia 0.8)
+ (via_drill 0.4)
+ (uvia_dia 0.3)
+ (uvia_drill 0.1)
+ )
+
+ (gr_line (start 55 145) (end 214.85 145) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 55 45.15) (end 55 145) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 214.84 45.15) (end 55 45.15) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 214.85 145) (end 214.85 45.15) (angle 90) (layer Edge.Cuts) (width 0.15))
+
+)