CD4081 is AND gate IC.

11 files changed, 1081 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081-cache.lib b/library/SubcircuitLibrary/CD_4081/CD_4081-cache.lib
new file mode 100644
index 00000000..6c512720
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/CD_4081-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.cir b/library/SubcircuitLibrary/CD_4081/CD_4081.cir
new file mode 100644
index 00000000..03101ff9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/CD_4081.cir
@@ -0,0 +1,35 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4081\CD_4081.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/30/22 21:25:36
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M10  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+M8  Net-_M10-Pad2_ Net-_M6-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M2  Net-_M10-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M12  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M5  Net-_M10-Pad2_ Net-_M2-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_N		
+M6  Net-_M5-Pad3_ Net-_M6-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+M23  Net-_M23-Pad1_ Net-_M14-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+M20  Net-_M14-Pad1_ Net-_M18-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M14  Net-_M14-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M24  Net-_M23-Pad1_ Net-_M14-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M17  Net-_M14-Pad1_ Net-_M14-Pad2_ Net-_M17-Pad3_ Net-_M17-Pad3_ eSim_MOS_N		
+M18  Net-_M17-Pad3_ Net-_M18-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+M9  Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+M7  Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M11  Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M3  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N		
+M4  Net-_M3-Pad3_ Net-_M4-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+M21  Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+M19  Net-_M13-Pad1_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M13  Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M22  Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P		
+M15  Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M15-Pad3_ Net-_M15-Pad3_ eSim_MOS_N		
+M16  Net-_M15-Pad3_ Net-_M16-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N		
+U1  Net-_M2-Pad2_ Net-_M6-Pad2_ Net-_M10-Pad1_ Net-_M23-Pad1_ Net-_M14-Pad2_ Net-_M18-Pad2_ Net-_M10-Pad3_ Net-_M13-Pad2_ Net-_M16-Pad2_ Net-_M21-Pad1_ Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M4-Pad2_ Net-_M1-Pad3_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.cir.out b/library/SubcircuitLibrary/CD_4081/CD_4081.cir.out
new file mode 100644
index 00000000..b4c78312
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/CD_4081.cir.out
@@ -0,0 +1,38 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd_4081\cd_4081.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m12 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m5 net-_m10-pad2_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1
+m6 net-_m5-pad3_ net-_m6-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m23 net-_m23-pad1_ net-_m14-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m24 net-_m23-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m17 net-_m14-pad1_ net-_m14-pad2_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m18-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m9 net-_m11-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m3-pad3_ net-_m4-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m21 net-_m21-pad1_ net-_m13-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m22 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m15 net-_m13-pad1_ net-_m13-pad2_ net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1
+m16 net-_m15-pad3_ net-_m16-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+* u1  net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m23-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m10-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m1-pad3_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.pro b/library/SubcircuitLibrary/CD_4081/CD_4081.pro
new file mode 100644
index 00000000..d7f78c3b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/CD_4081.pro
@@ -0,0 +1,71 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.sch b/library/SubcircuitLibrary/CD_4081/CD_4081.sch
new file mode 100644
index 00000000..7a89dcc8
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/CD_4081.sch
@@ -0,0 +1,745 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:CD_4081-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_N M10
+U 1 1 6294E1FE
+P 4000 4900
+F 0 "M10" H 4000 4750 50  0000 R CNN
+F 1 "eSim_MOS_N" H 4100 4850 50  0000 R CNN
+F 2 "" H 4300 4600 29  0000 C CNN
+F 3 "" H 4100 4700 60  0000 C CNN
+	1    4000 4900
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_P M8
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+F 2 "" H 3700 4550 29  0000 C CNN
+F 3 "" H 3500 4450 60  0000 C CNN
+	1    3450 4450
+	-1   0    0    1   
+$EndComp
+$Comp
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+F 2 "" H 2950 4550 29  0000 C CNN
+F 3 "" H 2750 4450 60  0000 C CNN
+	1    2700 4450
+	1    0    0    1   
+$EndComp
+$Comp
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+F 2 "" H 4300 4650 29  0000 C CNN
+F 3 "" H 4100 4550 60  0000 C CNN
+	1    4050 4550
+	1    0    0    1   
+$EndComp
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+F 2 "" H 3150 4600 29  0000 C CNN
+F 3 "" H 2950 4700 60  0000 C CNN
+	1    2850 4900
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 2 "" H 3150 5100 29  0000 C CNN
+F 3 "" H 2950 5200 60  0000 C CNN
+	1    2850 5400
+	1    0    0    -1  
+$EndComp
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+F 3 "" H 7200 4700 60  0000 C CNN
+	1    7100 4900
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 6294E205
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+	1    6550 4450
+	-1   0    0    1   
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+	1    0    0    1   
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+F 3 "" H 6050 4700 60  0000 C CNN
+	1    5950 4900
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 2 "" H 6250 5100 29  0000 C CNN
+F 3 "" H 6050 5200 60  0000 C CNN
+	1    5950 5400
+	1    0    0    -1  
+$EndComp
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+F 2 "" H 4300 2500 29  0000 C CNN
+F 3 "" H 4100 2600 60  0000 C CNN
+	1    4000 2800
+	1    0    0    -1  
+$EndComp
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+F 2 "" H 3700 2450 29  0000 C CNN
+F 3 "" H 3500 2350 60  0000 C CNN
+	1    3450 2350
+	-1   0    0    1   
+$EndComp
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+F 2 "" H 2950 2450 29  0000 C CNN
+F 3 "" H 2750 2350 60  0000 C CNN
+	1    2700 2350
+	1    0    0    1   
+$EndComp
+$Comp
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+F 0 "M11" H 4000 2500 50  0000 R CNN
+F 1 "eSim_MOS_P" H 4100 2600 50  0000 R CNN
+F 2 "" H 4300 2550 29  0000 C CNN
+F 3 "" H 4100 2450 60  0000 C CNN
+	1    4050 2450
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 6294E20E
+P 2850 2800
+F 0 "M3" H 2850 2650 50  0000 R CNN
+F 1 "eSim_MOS_N" H 2950 2750 50  0000 R CNN
+F 2 "" H 3150 2500 29  0000 C CNN
+F 3 "" H 2950 2600 60  0000 C CNN
+	1    2850 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M4
+U 1 1 6294E20F
+P 2850 3300
+F 0 "M4" H 2850 3150 50  0000 R CNN
+F 1 "eSim_MOS_N" H 2950 3250 50  0000 R CNN
+F 2 "" H 3150 3000 29  0000 C CNN
+F 3 "" H 2950 3100 60  0000 C CNN
+	1    2850 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M21
+U 1 1 6294E210
+P 7050 2800
+F 0 "M21" H 7050 2650 50  0000 R CNN
+F 1 "eSim_MOS_N" H 7150 2750 50  0000 R CNN
+F 2 "" H 7350 2500 29  0000 C CNN
+F 3 "" H 7150 2600 60  0000 C CNN
+	1    7050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_P M19
+U 1 1 6294E211
+P 6500 2350
+F 0 "M19" H 6450 2400 50  0000 R CNN
+F 1 "eSim_MOS_P" H 6550 2500 50  0000 R CNN
+F 2 "" H 6750 2450 29  0000 C CNN
+F 3 "" H 6550 2350 60  0000 C CNN
+	1    6500 2350
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_MOS_P M13
+U 1 1 6294E212
+P 5750 2350
+F 0 "M13" H 5700 2400 50  0000 R CNN
+F 1 "eSim_MOS_P" H 5800 2500 50  0000 R CNN
+F 2 "" H 6000 2450 29  0000 C CNN
+F 3 "" H 5800 2350 60  0000 C CNN
+	1    5750 2350
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_MOS_P M22
+U 1 1 6294E213
+P 7100 2450
+F 0 "M22" H 7050 2500 50  0000 R CNN
+F 1 "eSim_MOS_P" H 7150 2600 50  0000 R CNN
+F 2 "" H 7350 2550 29  0000 C CNN
+F 3 "" H 7150 2450 60  0000 C CNN
+	1    7100 2450
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_MOS_N M15
+U 1 1 6294E214
+P 5900 2800
+F 0 "M15" H 5900 2650 50  0000 R CNN
+F 1 "eSim_MOS_N" H 6000 2750 50  0000 R CNN
+F 2 "" H 6200 2500 29  0000 C CNN
+F 3 "" H 6000 2600 60  0000 C CNN
+	1    5900 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_N M16
+U 1 1 6294E215
+P 5900 3300
+F 0 "M16" H 5900 3150 50  0000 R CNN
+F 1 "eSim_MOS_N" H 6000 3250 50  0000 R CNN
+F 2 "" H 6200 3000 29  0000 C CNN
+F 3 "" H 6000 3100 60  0000 C CNN
+	1    5900 3300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2850 4250 7350 4250
+Wire Wire Line
+	2850 4650 3300 4650
+Wire Wire Line
+	3050 4650 3050 4900
+Connection ~ 3050 4650
+Wire Wire Line
+	3050 5300 3050 5400
+Wire Wire Line
+	3150 5750 3150 5800
+Wire Wire Line
+	3050 5800 7350 5800
+Wire Wire Line
+	3150 5250 3150 5300
+Wire Wire Line
+	3150 5300 3050 5300
+Wire Wire Line
+	3200 4300 3200 4250
+Connection ~ 3200 4250
+Wire Wire Line
+	2950 4300 2950 4250
+Connection ~ 2950 4250
+Wire Wire Line
+	4200 4350 4300 4350
+Wire Wire Line
+	4300 4350 4300 4400
+Wire Wire Line
+	4200 5300 4300 5300
+Wire Wire Line
+	4300 5300 4300 5250
+Wire Wire Line
+	4200 4750 4200 4900
+Wire Wire Line
+	3900 4550 3900 5100
+Wire Wire Line
+	3050 4800 3900 4800
+Connection ~ 3050 4800
+Connection ~ 3900 4800
+Wire Wire Line
+	2550 4450 2550 5100
+Wire Wire Line
+	2550 5100 2750 5100
+Wire Wire Line
+	3600 4450 3600 5400
+Wire Wire Line
+	3600 5400 2750 5400
+Wire Wire Line
+	2750 5400 2750 5600
+Wire Wire Line
+	2550 4750 2200 4750
+Connection ~ 2550 4750
+Wire Wire Line
+	2750 5500 2200 5500
+Connection ~ 2750 5500
+Wire Wire Line
+	4200 4800 4500 4800
+Connection ~ 4200 4800
+Wire Wire Line
+	5950 4650 6400 4650
+Wire Wire Line
+	6150 4650 6150 4900
+Connection ~ 6150 4650
+Wire Wire Line
+	6150 5300 6150 5400
+Wire Wire Line
+	6250 5800 6250 5750
+Wire Wire Line
+	6250 5250 6250 5300
+Wire Wire Line
+	6250 5300 6150 5300
+Wire Wire Line
+	6300 4300 6300 4250
+Connection ~ 6300 4250
+Wire Wire Line
+	6050 4300 6050 4250
+Connection ~ 6050 4250
+Wire Wire Line
+	7300 4350 7400 4350
+Wire Wire Line
+	7400 4350 7400 4400
+Wire Wire Line
+	7300 5300 7400 5300
+Wire Wire Line
+	7400 5300 7400 5250
+Wire Wire Line
+	7300 4750 7300 4900
+Wire Wire Line
+	7000 4550 7000 5100
+Wire Wire Line
+	6150 4800 7000 4800
+Connection ~ 6150 4800
+Connection ~ 7000 4800
+Wire Wire Line
+	5650 4450 5650 5100
+Wire Wire Line
+	5650 5100 5850 5100
+Wire Wire Line
+	6700 4450 6700 5400
+Wire Wire Line
+	6700 5400 5850 5400
+Wire Wire Line
+	5850 5400 5850 5600
+Wire Wire Line
+	5650 4750 5300 4750
+Connection ~ 5650 4750
+Wire Wire Line
+	5850 5500 5300 5500
+Connection ~ 5850 5500
+Wire Wire Line
+	7300 4800 7600 4800
+Connection ~ 7300 4800
+Wire Wire Line
+	2850 2150 7300 2150
+Wire Wire Line
+	2850 2550 3300 2550
+Wire Wire Line
+	3050 2550 3050 2800
+Connection ~ 3050 2550
+Wire Wire Line
+	3050 3200 3050 3300
+Wire Wire Line
+	3150 3650 3150 3700
+Wire Wire Line
+	3050 3700 7300 3700
+Wire Wire Line
+	3150 3150 3150 3200
+Wire Wire Line
+	3150 3200 3050 3200
+Wire Wire Line
+	3200 2200 3200 2150
+Connection ~ 3200 2150
+Wire Wire Line
+	2950 2200 2950 2150
+Connection ~ 2950 2150
+Wire Wire Line
+	4200 2250 4300 2250
+Wire Wire Line
+	4300 2250 4300 2300
+Wire Wire Line
+	4200 3200 4300 3200
+Wire Wire Line
+	4300 3200 4300 3150
+Wire Wire Line
+	4200 2650 4200 2800
+Wire Wire Line
+	3900 2450 3900 3000
+Wire Wire Line
+	3050 2700 3900 2700
+Connection ~ 3050 2700
+Connection ~ 3900 2700
+Wire Wire Line
+	2550 2350 2550 3000
+Wire Wire Line
+	2550 3000 2750 3000
+Wire Wire Line
+	3600 2350 3600 3300
+Wire Wire Line
+	3600 3300 2750 3300
+Wire Wire Line
+	2750 3300 2750 3500
+Wire Wire Line
+	2550 2650 2200 2650
+Connection ~ 2550 2650
+Wire Wire Line
+	2750 3400 2200 3400
+Connection ~ 2750 3400
+Wire Wire Line
+	4200 2700 4500 2700
+Connection ~ 4200 2700
+Wire Wire Line
+	5900 2550 6350 2550
+Wire Wire Line
+	6100 2550 6100 2800
+Connection ~ 6100 2550
+Wire Wire Line
+	6100 3200 6100 3300
+Wire Wire Line
+	6200 3700 6200 3650
+Wire Wire Line
+	6200 3150 6200 3200
+Wire Wire Line
+	6200 3200 6100 3200
+Wire Wire Line
+	6250 2200 6250 2150
+Connection ~ 6250 2150
+Wire Wire Line
+	6000 2200 6000 2150
+Connection ~ 6000 2150
+Wire Wire Line
+	7250 2250 7350 2250
+Wire Wire Line
+	7350 2250 7350 2300
+Wire Wire Line
+	7250 3200 7350 3200
+Wire Wire Line
+	7350 3200 7350 3150
+Wire Wire Line
+	7250 2650 7250 2800
+Wire Wire Line
+	6950 2450 6950 3000
+Wire Wire Line
+	6100 2700 6950 2700
+Connection ~ 6100 2700
+Connection ~ 6950 2700
+Wire Wire Line
+	5600 2350 5600 3000
+Wire Wire Line
+	5600 3000 5800 3000
+Wire Wire Line
+	6650 2350 6650 3300
+Wire Wire Line
+	6650 3300 5800 3300
+Wire Wire Line
+	5800 3300 5800 3500
+Wire Wire Line
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+Connection ~ 5600 2650
+Wire Wire Line
+	5800 3400 5250 3400
+Connection ~ 5800 3400
+Wire Wire Line
+	7250 2700 7550 2700
+Connection ~ 7250 2700
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+Connection ~ 3300 4250
+Connection ~ 5900 2150
+Connection ~ 3300 2150
+Connection ~ 6100 3700
+Connection ~ 3150 3700
+Connection ~ 6150 5800
+Connection ~ 3150 5800
+Wire Wire Line
+	4950 3700 4950 6050
+Connection ~ 4950 5800
+Connection ~ 4950 3700
+Wire Wire Line
+	4800 1850 4800 4250
+Connection ~ 4800 4250
+Connection ~ 4800 2150
+Wire Wire Line
+	7300 2150 7300 2250
+Connection ~ 6350 2150
+Connection ~ 7300 2250
+Wire Wire Line
+	7300 3700 7300 3200
+Connection ~ 6200 3700
+Connection ~ 7300 3200
+Wire Wire Line
+	4250 3200 4250 3700
+Connection ~ 4250 3700
+Connection ~ 4250 3200
+Wire Wire Line
+	4250 2250 4250 2150
+Connection ~ 4250 2150
+Connection ~ 4250 2250
+Wire Wire Line
+	4250 4350 4250 4250
+Connection ~ 4250 4250
+Connection ~ 4250 4350
+Wire Wire Line
+	4250 5300 4250 5800
+Connection ~ 4250 5800
+Connection ~ 4250 5300
+Wire Wire Line
+	7350 4250 7350 4350
+Connection ~ 6400 4250
+Connection ~ 7350 4350
+Wire Wire Line
+	7350 5800 7350 5300
+Connection ~ 6250 5800
+Connection ~ 7350 5300
+$Comp
+L PORT U1
+U 1 1 629516D8
+P 1950 4750
+F 0 "U1" H 2000 4850 30  0000 C CNN
+F 1 "PORT" H 1950 4750 30  0000 C CNN
+F 2 "" H 1950 4750 60  0000 C CNN
+F 3 "" H 1950 4750 60  0000 C CNN
+	1    1950 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 62951745
+P 1950 5500
+F 0 "U1" H 2000 5600 30  0000 C CNN
+F 1 "PORT" H 1950 5500 30  0000 C CNN
+F 2 "" H 1950 5500 60  0000 C CNN
+F 3 "" H 1950 5500 60  0000 C CNN
+	2    1950 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 629517B4
+P 4750 4800
+F 0 "U1" H 4800 4900 30  0000 C CNN
+F 1 "PORT" H 4750 4800 30  0000 C CNN
+F 2 "" H 4750 4800 60  0000 C CNN
+F 3 "" H 4750 4800 60  0000 C CNN
+	3    4750 4800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 62951900
+P 7850 4800
+F 0 "U1" H 7900 4900 30  0000 C CNN
+F 1 "PORT" H 7850 4800 30  0000 C CNN
+F 2 "" H 7850 4800 60  0000 C CNN
+F 3 "" H 7850 4800 60  0000 C CNN
+	4    7850 4800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 62951991
+P 5050 4750
+F 0 "U1" H 5100 4850 30  0000 C CNN
+F 1 "PORT" H 5050 4750 30  0000 C CNN
+F 2 "" H 5050 4750 60  0000 C CNN
+F 3 "" H 5050 4750 60  0000 C CNN
+	5    5050 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 629519FC
+P 5050 5500
+F 0 "U1" H 5100 5600 30  0000 C CNN
+F 1 "PORT" H 5050 5500 30  0000 C CNN
+F 2 "" H 5050 5500 60  0000 C CNN
+F 3 "" H 5050 5500 60  0000 C CNN
+	6    5050 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6295226B
+P 4700 6050
+F 0 "U1" H 4750 6150 30  0000 C CNN
+F 1 "PORT" H 4700 6050 30  0000 C CNN
+F 2 "" H 4700 6050 60  0000 C CNN
+F 3 "" H 4700 6050 60  0000 C CNN
+	7    4700 6050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 62952B28
+P 5000 2650
+F 0 "U1" H 5050 2750 30  0000 C CNN
+F 1 "PORT" H 5000 2650 30  0000 C CNN
+F 2 "" H 5000 2650 60  0000 C CNN
+F 3 "" H 5000 2650 60  0000 C CNN
+	8    5000 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 62952BC3
+P 5000 3400
+F 0 "U1" H 5050 3500 30  0000 C CNN
+F 1 "PORT" H 5000 3400 30  0000 C CNN
+F 2 "" H 5000 3400 60  0000 C CNN
+F 3 "" H 5000 3400 60  0000 C CNN
+	9    5000 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 62952C34
+P 7800 2700
+F 0 "U1" H 7850 2800 30  0000 C CNN
+F 1 "PORT" H 7800 2700 30  0000 C CNN
+F 2 "" H 7800 2700 60  0000 C CNN
+F 3 "" H 7800 2700 60  0000 C CNN
+	10   7800 2700
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 62952CD1
+P 4750 2700
+F 0 "U1" H 4800 2800 30  0000 C CNN
+F 1 "PORT" H 4750 2700 30  0000 C CNN
+F 2 "" H 4750 2700 60  0000 C CNN
+F 3 "" H 4750 2700 60  0000 C CNN
+	11   4750 2700
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 62952D8E
+P 1950 2650
+F 0 "U1" H 2000 2750 30  0000 C CNN
+F 1 "PORT" H 1950 2650 30  0000 C CNN
+F 2 "" H 1950 2650 60  0000 C CNN
+F 3 "" H 1950 2650 60  0000 C CNN
+	12   1950 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 62952E35
+P 1950 3400
+F 0 "U1" H 2000 3500 30  0000 C CNN
+F 1 "PORT" H 1950 3400 30  0000 C CNN
+F 2 "" H 1950 3400 60  0000 C CNN
+F 3 "" H 1950 3400 60  0000 C CNN
+	13   1950 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 62953458
+P 4550 1850
+F 0 "U1" H 4600 1950 30  0000 C CNN
+F 1 "PORT" H 4550 1850 30  0000 C CNN
+F 2 "" H 4550 1850 60  0000 C CNN
+F 3 "" H 4550 1850 60  0000 C CNN
+	14   4550 1850
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.sub b/library/SubcircuitLibrary/CD_4081/CD_4081.sub
new file mode 100644
index 00000000..f5050506
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/CD_4081.sub
@@ -0,0 +1,32 @@
+* Subcircuit CD_4081
+.subckt CD_4081 net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m23-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m10-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m1-pad3_ 
+* c:\fossee\esim\library\subcircuitlibrary\cd_4081\cd_4081.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m12 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m5 net-_m10-pad2_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1
+m6 net-_m5-pad3_ net-_m6-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m23 net-_m23-pad1_ net-_m14-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m24 net-_m23-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m17 net-_m14-pad1_ net-_m14-pad2_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1
+m18 net-_m17-pad3_ net-_m18-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m9 net-_m11-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m3-pad3_ net-_m4-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m21 net-_m21-pad1_ net-_m13-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m22 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1
+m15 net-_m13-pad1_ net-_m13-pad2_ net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1
+m16 net-_m15-pad3_ net-_m16-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1
+* Control Statements
+
+.ends CD_4081
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081_Previous_Values.xml b/library/SubcircuitLibrary/CD_4081/CD_4081_Previous_Values.xml
new file mode 100644
index 00000000..5166d2ba
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/CD_4081_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m12><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6><m23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m23><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m20><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m14><m24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m24><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m17><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m18><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m1><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m21><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m19><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m13><m22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m22><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m15><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m16></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib
new file mode 100644
index 00000000..51e9b119
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib
new file mode 100644
index 00000000..032b5b95
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/CD_4081/README.md b/library/SubcircuitLibrary/CD_4081/README.md
new file mode 100644
index 00000000..5e6b11c7
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/README.md
@@ -0,0 +1,34 @@
+
+# CD4081 IC
+
+It is 2-input AND Gate IC. CD4081 IC is designed with 180nm CMOS technology in eSim consisting four AND Gates. When both the inputs are HIGH then only output is HIGH, otherwise LOW.
+
+
+## Usage/Examples
+
+Logic buffers, inverters, and decoders
+
+Implementing logic circuits
+
+Signal conditioning
+
+Enable gate
+
+Inhibit gate
+
+Measurement of frequency
+
+## Documentation
+
+To know the details of CD4081 IC please go through with the documentation : [CD4081_datasheet](https://www.ti.com/lit/gpn/cd4081b)
+
+## Comments/Notes
+
+Please note this is a complete digital IC. It works fine at the time of simulation.
+
+## Contributer
+
+Name: Ankush Mondal
+Email: mondalankush369@gmail.com
+Year: 2022
+Position: FOSSEE Summer Fellow 2022
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD_4081/analysis b/library/SubcircuitLibrary/CD_4081/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD_4081/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file