diff options
author | saurabhb17 | 2020-03-18 14:26:36 +0530 |
---|---|---|
committer | saurabhb17 | 2020-03-18 14:26:36 +0530 |
commit | 50cc0a9c65834db636c502cde6548f9e3971600c (patch) | |
tree | 28faa109a0674593dfa190c00508e4680232d934 /library/SubcircuitLibrary/ua741 | |
parent | c967b3b3b27dc4e76ee2bb7a1820a97c5306b8d2 (diff) | |
download | eSim-50cc0a9c65834db636c502cde6548f9e3971600c.tar.gz eSim-50cc0a9c65834db636c502cde6548f9e3971600c.tar.bz2 eSim-50cc0a9c65834db636c502cde6548f9e3971600c.zip |
Subcircuit libs cleanup
Diffstat (limited to 'library/SubcircuitLibrary/ua741')
-rw-r--r-- | library/SubcircuitLibrary/ua741/ua741-cache.lib | 127 | ||||
-rw-r--r-- | library/SubcircuitLibrary/ua741/ua741.pro | 77 | ||||
-rw-r--r-- | library/SubcircuitLibrary/ua741/ua741.sch | 218 |
3 files changed, 252 insertions, 170 deletions
diff --git a/library/SubcircuitLibrary/ua741/ua741-cache.lib b/library/SubcircuitLibrary/ua741/ua741-cache.lib new file mode 100644 index 00000000..a330f429 --- /dev/null +++ b/library/SubcircuitLibrary/ua741/ua741-cache.lib @@ -0,0 +1,127 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ua741/ua741.pro b/library/SubcircuitLibrary/ua741/ua741.pro index 5dbb81a5..c7b1d67b 100644 --- a/library/SubcircuitLibrary/ua741/ua741.pro +++ b/library/SubcircuitLibrary/ua741/ua741.pro @@ -1,72 +1,17 @@ -update=Monday 17 December 2012 06:14:06 PM IST +update=Wed Mar 18 14:21:29 2020 last_client=eeschema [eeschema] version=1 LibDir=/home/yogesh/FreeEDA/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 [eeschema/libraries] LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice +LibName2=eSim_Devices +LibName3=eSim_User +LibName4=eSim_Subckt +LibName5=eSim_Sources +LibName6=eSim_Power +LibName7=eSim_Plot +LibName8=eSim_Miscellaneous +LibName9=eSim_Hybrid +LibName10=eSim_Digital +LibName11=eSim_Analog diff --git a/library/SubcircuitLibrary/ua741/ua741.sch b/library/SubcircuitLibrary/ua741/ua741.sch index 7dfc5e1a..b06dcc17 100644 --- a/library/SubcircuitLibrary/ua741/ua741.sch +++ b/library/SubcircuitLibrary/ua741/ua741.sch @@ -1,46 +1,18 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +EESchema Schematic File Version 2 LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 +LIBS:eSim_Devices +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Analog +EELAYER 25 0 EELAYER END -$Descr A4 11700 8267 +$Descr A4 11693 8268 encoding utf-8 Sheet 1 1 Title "" @@ -68,6 +40,8 @@ U 6 1 5082C027 P 6250 2500 F 0 "U1" H 6250 2450 30 0000 C CNN F 1 "PORT" H 6250 2500 30 0000 C CNN +F 2 "" H 6250 2500 60 0001 C CNN +F 3 "" H 6250 2500 60 0001 C CNN 6 6250 2500 -1 0 0 1 $EndComp @@ -77,6 +51,8 @@ U 2 1 5082C011 P 2300 3100 F 0 "U1" H 2300 3050 30 0000 C CNN F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0001 C CNN +F 3 "" H 2300 3100 60 0001 C CNN 2 2300 3100 1 0 0 -1 $EndComp @@ -86,9 +62,57 @@ U 3 1 5082C00B P 2250 2600 F 0 "U1" H 2250 2550 30 0000 C CNN F 1 "PORT" H 2250 2600 30 0000 C CNN +F 2 "" H 2250 2600 60 0001 C CNN +F 3 "" H 2250 2600 60 0001 C CNN 3 2250 2600 1 0 0 -1 $EndComp +$Comp +L PWR_FLAG #FLG1 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG1" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN +F 2 "" H 3450 3200 60 0001 C CNN +F 3 "" H 3450 3200 60 0001 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN +F 2 "" H 5200 2900 60 0001 C CNN +F 3 "" H 5200 2900 60 0001 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR1 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR1" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN +F 2 "" H 3700 3400 60 0001 C CNN +F 3 "" H 3700 3400 60 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN +F 2 "" H 3650 2850 60 0001 C CNN +F 3 "" H 3650 2850 60 0001 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +Text Notes 2600 2900 0 60 ~ 0 +2e6\n Connection ~ 3700 3200 Wire Wire Line 3450 3200 3700 3200 @@ -102,7 +126,7 @@ Wire Wire Line 5000 3300 5000 2950 Connection ~ 3700 3300 Wire Wire Line - 4550 3300 4550 3100 + 4550 3000 4550 3300 Wire Wire Line 3900 2500 3700 2500 Wire Wire Line @@ -141,79 +165,65 @@ Connection ~ 4550 2500 Wire Wire Line 5250 2600 5250 2500 Wire Wire Line - 5250 2500 5350 2500 + 5250 2500 5400 2500 Wire Wire Line - 5850 2500 6000 2500 + 5700 2500 6000 2500 $Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 +L resistor Rin1 +U 1 1 5E71E232 +P 2950 2900 +F 0 "Rin1" H 3000 3030 50 0000 C CNN +F 1 "2e6" H 3000 2850 50 0000 C CNN +F 2 "" H 3000 2880 30 0000 C CNN +F 3 "" V 3000 2950 30 0000 C CNN + 1 2950 2900 0 1 1 0 $EndComp +Wire Wire Line + 3000 2600 3000 2800 $Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 +L resistor Rbw1 +U 1 1 5E71E326 +P 4050 2100 +F 0 "Rbw1" H 4100 2230 50 0000 C CNN +F 1 "0.5e6" H 4100 2050 50 0000 C CNN +F 2 "" H 4100 2080 30 0000 C CNN +F 3 "" V 4100 2150 30 0000 C CNN + 1 4050 2100 1 0 0 -1 $EndComp +Wire Wire Line + 3900 2500 3900 2050 +Wire Wire Line + 3900 2050 3950 2050 +Wire Wire Line + 4250 2050 4400 2050 +Wire Wire Line + 4400 2050 4400 2500 $Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 +L capacitor Cbw1 +U 1 1 5E71E45C +P 4550 2850 +F 0 "Cbw1" H 4575 2950 50 0000 L CNN +F 1 "31.85e-9" H 4575 2750 50 0000 L CNN +F 2 "" H 4588 2700 30 0000 C CNN +F 3 "" H 4550 2850 60 0000 C CNN + 1 4550 2850 1 0 0 -1 $EndComp $Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 +L resistor Rout1 +U 1 1 5E71E59C +P 5500 2250 +F 0 "Rout1" H 5550 2380 50 0000 C CNN +F 1 "75" H 5550 2200 50 0000 C CNN +F 2 "" H 5550 2230 30 0000 C CNN +F 3 "" V 5550 2300 30 0000 C CNN + 1 5500 2250 1 0 0 -1 $EndComp +Wire Wire Line + 5400 2500 5400 2200 +Wire Wire Line + 5700 2200 5700 2500 $EndSCHEMATC |