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authorrahulp132020-02-21 12:36:46 +0530
committerrahulp132020-02-21 12:36:46 +0530
commit47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch)
tree55aefefe974f151de76c6a2dbe8df3b4c3393bbe /library/SubcircuitLibrary/full_sub/half_sub.sub
parent453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff)
downloadeSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz
eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2
eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip
restructured eSim libraries
Diffstat (limited to 'library/SubcircuitLibrary/full_sub/half_sub.sub')
-rw-r--r--library/SubcircuitLibrary/full_sub/half_sub.sub18
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diff --git a/library/SubcircuitLibrary/full_sub/half_sub.sub b/library/SubcircuitLibrary/full_sub/half_sub.sub
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+* Subcircuit half_sub
+.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
+* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_sub \ No newline at end of file