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| author | Rahul P | 2020-03-04 17:01:11 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-04 17:01:11 +0530 |
| commit | 8ffe81b36caa259151978de0434e4e0c5c32d217 (patch) | |
| tree | 32202454d13dfabbf6556e98987f2a9632619ea9 /library/SubcircuitLibrary/full_sub/full_sub.sub | |
| parent | e40317e709c220176fc5b7edf23d4434504335b0 (diff) | |
| parent | 13f3bcfda9416624cebbf5705de398e8efcad344 (diff) | |
| download | eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2 eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.zip | |
Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'library/SubcircuitLibrary/full_sub/full_sub.sub')
| -rw-r--r-- | library/SubcircuitLibrary/full_sub/full_sub.sub | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/full_sub/full_sub.sub b/library/SubcircuitLibrary/full_sub/full_sub.sub new file mode 100644 index 00000000..9c9dcc5a --- /dev/null +++ b/library/SubcircuitLibrary/full_sub/full_sub.sub @@ -0,0 +1,13 @@ +* Subcircuit full_sub +.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_sub
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