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authorRahul P2020-03-04 17:01:11 +0530
committerGitHub2020-03-04 17:01:11 +0530
commit8ffe81b36caa259151978de0434e4e0c5c32d217 (patch)
tree32202454d13dfabbf6556e98987f2a9632619ea9 /library/SubcircuitLibrary/full_sub/full_sub.cir.out
parente40317e709c220176fc5b7edf23d4434504335b0 (diff)
parent13f3bcfda9416624cebbf5705de398e8efcad344 (diff)
downloadeSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz
eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2
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Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'library/SubcircuitLibrary/full_sub/full_sub.cir.out')
-rw-r--r--library/SubcircuitLibrary/full_sub/full_sub.cir.out19
1 files changed, 19 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/full_sub/full_sub.cir.out b/library/SubcircuitLibrary/full_sub/full_sub.cir.out
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+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
+
+.include half_sub.sub
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
+* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port
+x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
+x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
+a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end