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| author | rahulp13 | 2020-02-21 12:36:46 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-21 12:36:46 +0530 |
| commit | 47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch) | |
| tree | 55aefefe974f151de76c6a2dbe8df3b4c3393bbe /library/SubcircuitLibrary/full_adder/full_adder.sub | |
| parent | 453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff) | |
| download | eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2 eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip | |
restructured eSim libraries
Diffstat (limited to 'library/SubcircuitLibrary/full_adder/full_adder.sub')
| -rw-r--r-- | library/SubcircuitLibrary/full_adder/full_adder.sub | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/full_adder/full_adder.sub b/library/SubcircuitLibrary/full_adder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
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