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author | Rahul P | 2020-03-04 17:01:11 +0530 |
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committer | GitHub | 2020-03-04 17:01:11 +0530 |
commit | 8ffe81b36caa259151978de0434e4e0c5c32d217 (patch) | |
tree | 32202454d13dfabbf6556e98987f2a9632619ea9 /library/SubcircuitLibrary/full_adder/full_adder.cir | |
parent | e40317e709c220176fc5b7edf23d4434504335b0 (diff) | |
parent | 13f3bcfda9416624cebbf5705de398e8efcad344 (diff) | |
download | eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2 eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.zip |
Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'library/SubcircuitLibrary/full_adder/full_adder.cir')
-rw-r--r-- | library/SubcircuitLibrary/full_adder/full_adder.cir | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/full_adder/full_adder.cir b/library/SubcircuitLibrary/full_adder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/library/SubcircuitLibrary/full_adder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end |