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| author | Aditya Minocha | 2024-08-25 21:34:06 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 21:34:06 +0530 |
| commit | 7f60ce39c1e72fff19153772e66a628f9678e5c9 (patch) | |
| tree | 34df2c39041c02ff50dc5fbc0aecf1d1298305a5 /library/SubcircuitLibrary/SN54HC148/4_and.cir | |
| parent | 4148cefab1bccb6c2cd4ae3606e5450cf090dac0 (diff) | |
| download | eSim-7f60ce39c1e72fff19153772e66a628f9678e5c9.tar.gz eSim-7f60ce39c1e72fff19153772e66a628f9678e5c9.tar.bz2 eSim-7f60ce39c1e72fff19153772e66a628f9678e5c9.zip | |
SN54HC148 IC - 8:3 Priority Encoder
Diffstat (limited to 'library/SubcircuitLibrary/SN54HC148/4_and.cir')
| -rw-r--r-- | library/SubcircuitLibrary/SN54HC148/4_and.cir | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN54HC148/4_and.cir b/library/SubcircuitLibrary/SN54HC148/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/library/SubcircuitLibrary/SN54HC148/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
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