Merge pull request #303 from Rachith-H/master

Subcircuit Files for different IC's

8 files changed, 859 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN54180/SN54180-cache.lib b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib
new file mode 100644
index 00000000..27b0f7f2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib
@@ -0,0 +1,134 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir b/library/SubcircuitLibrary/SN54180/SN54180.cir
new file mode 100644
index 00000000..89146f7f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/SN54180.cir
@@ -0,0 +1,25 @@
+* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN54180\SN54180.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/07/25 23:03:34
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U2-Pad3_ d_xnor		
+U3  Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U3-Pad3_ d_xnor		
+U4  Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad3_ d_xnor		
+U5  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U5-Pad3_ d_xnor		
+U8  Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U10-Pad1_ d_xnor		
+U6  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_xor		
+U7  Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_xor		
+U9  Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_U1-Pad4_ Net-_U10-Pad3_ d_and		
+U11  Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U11-Pad3_ d_and		
+U12  Net-_U1-Pad3_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and		
+U13  Net-_U11-Pad1_ Net-_U1-Pad4_ Net-_U13-Pad3_ d_and		
+U14  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad5_ d_nor		
+U15  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U1-Pad6_ d_nor		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir.out b/library/SubcircuitLibrary/SN54180/SN54180.cir.out
new file mode 100644
index 00000000..18993e8b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/SN54180.cir.out
@@ -0,0 +1,68 @@
+* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir
+
+* u2  net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor
+* u3  net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor
+* u4  net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor
+* u5  net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor
+* u8  net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor
+* u9  net-_u10-pad1_ net-_u11-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and
+* u12  net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and
+* u13  net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and
+* u14  net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor
+* u15  net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5
+a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a8 net-_u10-pad1_ net-_u11-pad1_ u9
+a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11
+a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12
+a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13
+a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14
+a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54180/SN54180.pro b/library/SubcircuitLibrary/SN54180/SN54180.pro
new file mode 100644
index 00000000..f63b751e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/SN54180.pro
@@ -0,0 +1,69 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sch b/library/SubcircuitLibrary/SN54180/SN54180.sch
new file mode 100644
index 00000000..1534f8b2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/SN54180.sch
@@ -0,0 +1,499 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:SN54180-cache
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xnor U2
+U 1 1 677290B0
+P 6050 7300
+F 0 "U2" H 6050 7300 60  0000 C CNN
+F 1 "d_xnor" H 6100 7400 47  0000 C CNN
+F 2 "" H 6050 7300 60  0000 C CNN
+F 3 "" H 6050 7300 60  0000 C CNN
+	1    6050 7300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xnor U3
+U 1 1 677290E7
+P 6050 7750
+F 0 "U3" H 6050 7750 60  0000 C CNN
+F 1 "d_xnor" H 6100 7850 47  0000 C CNN
+F 2 "" H 6050 7750 60  0000 C CNN
+F 3 "" H 6050 7750 60  0000 C CNN
+	1    6050 7750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xnor U4
+U 1 1 67729137
+P 6050 8200
+F 0 "U4" H 6050 8200 60  0000 C CNN
+F 1 "d_xnor" H 6100 8300 47  0000 C CNN
+F 2 "" H 6050 8200 60  0000 C CNN
+F 3 "" H 6050 8200 60  0000 C CNN
+	1    6050 8200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xnor U5
+U 1 1 6772913D
+P 6050 8650
+F 0 "U5" H 6050 8650 60  0000 C CNN
+F 1 "d_xnor" H 6100 8750 47  0000 C CNN
+F 2 "" H 6050 8650 60  0000 C CNN
+F 3 "" H 6050 8650 60  0000 C CNN
+	1    6050 8650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xnor U8
+U 1 1 6772915D
+P 8600 7950
+F 0 "U8" H 8600 7950 60  0000 C CNN
+F 1 "d_xnor" H 8650 8050 47  0000 C CNN
+F 2 "" H 8600 7950 60  0000 C CNN
+F 3 "" H 8600 7950 60  0000 C CNN
+	1    8600 7950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xor U6
+U 1 1 677291A8
+P 7350 7500
+F 0 "U6" H 7350 7500 60  0000 C CNN
+F 1 "d_xor" H 7400 7600 47  0000 C CNN
+F 2 "" H 7350 7500 60  0000 C CNN
+F 3 "" H 7350 7500 60  0000 C CNN
+	1    7350 7500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_xor U7
+U 1 1 677291CD
+P 7350 8400
+F 0 "U7" H 7350 8400 60  0000 C CNN
+F 1 "d_xor" H 7400 8500 47  0000 C CNN
+F 2 "" H 7350 8400 60  0000 C CNN
+F 3 "" H 7350 8400 60  0000 C CNN
+	1    7350 8400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 67729482
+P 9800 7900
+F 0 "U9" H 9800 7800 60  0000 C CNN
+F 1 "d_inverter" H 9800 8050 60  0000 C CNN
+F 2 "" H 9850 7850 60  0000 C CNN
+F 3 "" H 9850 7850 60  0000 C CNN
+	1    9800 7900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U10
+U 1 1 67729715
+P 11450 7250
+F 0 "U10" H 11450 7250 60  0000 C CNN
+F 1 "d_and" H 11500 7350 60  0000 C CNN
+F 2 "" H 11450 7250 60  0000 C CNN
+F 3 "" H 11450 7250 60  0000 C CNN
+	1    11450 7250
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U11
+U 1 1 6772978A
+P 11450 7750
+F 0 "U11" H 11450 7750 60  0000 C CNN
+F 1 "d_and" H 11500 7850 60  0000 C CNN
+F 2 "" H 11450 7750 60  0000 C CNN
+F 3 "" H 11450 7750 60  0000 C CNN
+	1    11450 7750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U12
+U 1 1 677297EE
+P 11450 8200
+F 0 "U12" H 11450 8200 60  0000 C CNN
+F 1 "d_and" H 11500 8300 60  0000 C CNN
+F 2 "" H 11450 8200 60  0000 C CNN
+F 3 "" H 11450 8200 60  0000 C CNN
+	1    11450 8200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U13
+U 1 1 677297F4
+P 11450 8700
+F 0 "U13" H 11450 8700 60  0000 C CNN
+F 1 "d_and" H 11500 8800 60  0000 C CNN
+F 2 "" H 11450 8700 60  0000 C CNN
+F 3 "" H 11450 8700 60  0000 C CNN
+	1    11450 8700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U14
+U 1 1 67729834
+P 13400 7550
+F 0 "U14" H 13400 7550 60  0000 C CNN
+F 1 "d_nor" H 13450 7650 60  0000 C CNN
+F 2 "" H 13400 7550 60  0000 C CNN
+F 3 "" H 13400 7550 60  0000 C CNN
+	1    13400 7550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 677299D9
+P 13400 8450
+F 0 "U15" H 13400 8450 60  0000 C CNN
+F 1 "d_nor" H 13450 8550 60  0000 C CNN
+F 2 "" H 13400 8450 60  0000 C CNN
+F 3 "" H 13400 8450 60  0000 C CNN
+	1    13400 8450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5600 7200 4850 7200
+Wire Wire Line
+	5600 7300 4850 7300
+Wire Wire Line
+	5600 7650 4850 7650
+Wire Wire Line
+	5600 7750 4850 7750
+Wire Wire Line
+	5600 8100 4850 8100
+Wire Wire Line
+	5600 8200 4850 8200
+Wire Wire Line
+	5600 8550 4850 8550
+Wire Wire Line
+	5600 8650 4850 8650
+Wire Wire Line
+	6500 7250 6750 7250
+Wire Wire Line
+	6750 7250 6750 7400
+Wire Wire Line
+	6750 7400 6900 7400
+Wire Wire Line
+	6900 7500 6750 7500
+Wire Wire Line
+	6750 7500 6750 7700
+Wire Wire Line
+	6750 7700 6500 7700
+Wire Wire Line
+	6500 8150 6700 8150
+Wire Wire Line
+	6700 8150 6700 8300
+Wire Wire Line
+	6700 8300 6900 8300
+Wire Wire Line
+	6900 8400 6700 8400
+Wire Wire Line
+	6700 8400 6700 8600
+Wire Wire Line
+	6700 8600 6500 8600
+Wire Wire Line
+	7800 7450 8000 7450
+Wire Wire Line
+	8000 7450 8000 7850
+Wire Wire Line
+	8000 7850 8150 7850
+Wire Wire Line
+	8150 7950 8000 7950
+Wire Wire Line
+	8000 7950 8000 8350
+Wire Wire Line
+	8000 8350 7800 8350
+Wire Wire Line
+	9050 7900 9500 7900
+Wire Wire Line
+	11000 7150 9300 7150
+Wire Wire Line
+	9300 7150 9300 8200
+Connection ~ 9300 7900
+Wire Wire Line
+	9300 8200 11000 8200
+Wire Wire Line
+	10350 7250 11000 7250
+Wire Wire Line
+	10350 7250 10350 9350
+Wire Wire Line
+	10350 8700 11000 8700
+Wire Wire Line
+	11000 7650 10550 7650
+Wire Wire Line
+	10550 7650 10550 8600
+Wire Wire Line
+	10550 8600 11000 8600
+Wire Wire Line
+	11000 7750 10800 7750
+Wire Wire Line
+	10800 7750 10800 9550
+Wire Wire Line
+	10800 8100 11000 8100
+Wire Wire Line
+	10100 7900 10550 7900
+Connection ~ 10550 7900
+Wire Wire Line
+	10350 9350 4850 9350
+Connection ~ 10350 8700
+Wire Wire Line
+	10800 9550 4850 9550
+Connection ~ 10800 8100
+Wire Wire Line
+	11900 7200 12500 7200
+Wire Wire Line
+	12500 7200 12500 7450
+Wire Wire Line
+	12500 7450 12950 7450
+Wire Wire Line
+	12500 7550 12950 7550
+Wire Wire Line
+	12500 7550 12500 7700
+Wire Wire Line
+	12500 7700 11900 7700
+Wire Wire Line
+	11900 8150 12500 8150
+Wire Wire Line
+	12500 8150 12500 8350
+Wire Wire Line
+	12500 8350 12950 8350
+Wire Wire Line
+	12950 8450 12500 8450
+Wire Wire Line
+	12500 8450 12500 8650
+Wire Wire Line
+	12500 8650 11900 8650
+Wire Wire Line
+	13850 7500 14550 7500
+Wire Wire Line
+	13850 8400 14550 8400
+$Comp
+L PORT U1
+U 1 1 677964E3
+P 4600 8550
+F 0 "U1" H 4650 8650 30  0000 C CNN
+F 1 "PORT" H 4600 8550 30  0000 C CNN
+F 2 "" H 4600 8550 60  0000 C CNN
+F 3 "" H 4600 8550 60  0000 C CNN
+	1    4600 8550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 677965B0
+P 4600 8750
+F 0 "U1" H 4650 8850 30  0000 C CNN
+F 1 "PORT" H 4600 8750 30  0000 C CNN
+F 2 "" H 4600 8750 60  0000 C CNN
+F 3 "" H 4600 8750 60  0000 C CNN
+	2    4600 8750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 8650 4850 8750
+$Comp
+L PORT U1
+U 3 1 6779664F
+P 4600 9550
+F 0 "U1" H 4650 9650 30  0000 C CNN
+F 1 "PORT" H 4600 9550 30  0000 C CNN
+F 2 "" H 4600 9550 60  0000 C CNN
+F 3 "" H 4600 9550 60  0000 C CNN
+	3    4600 9550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 67796694
+P 4600 9350
+F 0 "U1" H 4650 9450 30  0000 C CNN
+F 1 "PORT" H 4600 9350 30  0000 C CNN
+F 2 "" H 4600 9350 60  0000 C CNN
+F 3 "" H 4600 9350 60  0000 C CNN
+	4    4600 9350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 677975B7
+P 14800 7500
+F 0 "U1" H 14850 7600 30  0000 C CNN
+F 1 "PORT" H 14800 7500 30  0000 C CNN
+F 2 "" H 14800 7500 60  0000 C CNN
+F 3 "" H 14800 7500 60  0000 C CNN
+	5    14800 7500
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6779764E
+P 14800 8400
+F 0 "U1" H 14850 8500 30  0000 C CNN
+F 1 "PORT" H 14800 8400 30  0000 C CNN
+F 2 "" H 14800 8400 60  0000 C CNN
+F 3 "" H 14800 8400 60  0000 C CNN
+	6    14800 8400
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 67798A6F
+P 4600 7200
+F 0 "U1" H 4650 7300 30  0000 C CNN
+F 1 "PORT" H 4600 7200 30  0000 C CNN
+F 2 "" H 4600 7200 60  0000 C CNN
+F 3 "" H 4600 7200 60  0000 C CNN
+	8    4600 7200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 67798ABE
+P 4600 7400
+F 0 "U1" H 4650 7500 30  0000 C CNN
+F 1 "PORT" H 4600 7400 30  0000 C CNN
+F 2 "" H 4600 7400 60  0000 C CNN
+F 3 "" H 4600 7400 60  0000 C CNN
+	9    4600 7400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 67798B09
+P 4200 7550
+F 0 "U1" H 4250 7650 30  0000 C CNN
+F 1 "PORT" H 4200 7550 30  0000 C CNN
+F 2 "" H 4200 7550 60  0000 C CNN
+F 3 "" H 4200 7550 60  0000 C CNN
+	10   4200 7550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 67798B62
+P 4200 7800
+F 0 "U1" H 4250 7900 30  0000 C CNN
+F 1 "PORT" H 4200 7800 30  0000 C CNN
+F 2 "" H 4200 7800 60  0000 C CNN
+F 3 "" H 4200 7800 60  0000 C CNN
+	11   4200 7800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 67798BAD
+P 4450 8000
+F 0 "U1" H 4500 8100 30  0000 C CNN
+F 1 "PORT" H 4450 8000 30  0000 C CNN
+F 2 "" H 4450 8000 60  0000 C CNN
+F 3 "" H 4450 8000 60  0000 C CNN
+	12   4450 8000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 67798BFE
+P 4450 8250
+F 0 "U1" H 4500 8350 30  0000 C CNN
+F 1 "PORT" H 4450 8250 30  0000 C CNN
+F 2 "" H 4450 8250 60  0000 C CNN
+F 3 "" H 4450 8250 60  0000 C CNN
+	13   4450 8250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4450 7550 4850 7550
+Wire Wire Line
+	4850 7550 4850 7650
+Wire Wire Line
+	4450 7800 4850 7800
+Wire Wire Line
+	4850 7800 4850 7750
+Wire Wire Line
+	4850 7300 4850 7400
+Wire Wire Line
+	4700 8000 4850 8000
+Wire Wire Line
+	4850 8000 4850 8100
+Wire Wire Line
+	4700 8250 4850 8250
+Wire Wire Line
+	4850 8250 4850 8200
+$Comp
+L PORT U1
+U 7 1 677A3419
+P 5650 10400
+F 0 "U1" H 5700 10500 30  0000 C CNN
+F 1 "PORT" H 5650 10400 30  0000 C CNN
+F 2 "" H 5650 10400 60  0000 C CNN
+F 3 "" H 5650 10400 60  0000 C CNN
+	7    5650 10400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 677A353F
+P 5650 10650
+F 0 "U1" H 5700 10750 30  0000 C CNN
+F 1 "PORT" H 5650 10650 30  0000 C CNN
+F 2 "" H 5650 10650 60  0000 C CNN
+F 3 "" H 5650 10650 60  0000 C CNN
+	14   5650 10650
+	1    0    0    -1  
+$EndComp
+NoConn ~ 5900 10400
+NoConn ~ 5900 10650
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sub b/library/SubcircuitLibrary/SN54180/SN54180.sub
new file mode 100644
index 00000000..34693793
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/SN54180.sub
@@ -0,0 +1,62 @@
+* Subcircuit SN54180
+.subckt SN54180 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir
+* u2  net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor
+* u3  net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor
+* u4  net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor
+* u5  net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor
+* u8  net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor
+* u9  net-_u10-pad1_ net-_u11-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and
+* u12  net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and
+* u13  net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and
+* u14  net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor
+* u15  net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor
+a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5
+a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a8 net-_u10-pad1_ net-_u11-pad1_ u9
+a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11
+a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12
+a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13
+a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14
+a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_xor, NgSpice Name: d_xor
+.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends SN54180
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml
new file mode 100644
index 00000000..a66526b3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_xnor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_xnor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u5><u8 name="type">d_xnor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u8><u6 name="type">d_xor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54180/analysis b/library/SubcircuitLibrary/SN54180/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54180/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file