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| author | Rahul P | 2020-03-04 17:01:11 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-04 17:01:11 +0530 |
| commit | 8ffe81b36caa259151978de0434e4e0c5c32d217 (patch) | |
| tree | 32202454d13dfabbf6556e98987f2a9632619ea9 /library/SubcircuitLibrary/4012/4012.sub | |
| parent | e40317e709c220176fc5b7edf23d4434504335b0 (diff) | |
| parent | 13f3bcfda9416624cebbf5705de398e8efcad344 (diff) | |
| download | eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.gz eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.tar.bz2 eSim-8ffe81b36caa259151978de0434e4e0c5c32d217.zip | |
Merge pull request #132 from rahulp13/master
major changes
Diffstat (limited to 'library/SubcircuitLibrary/4012/4012.sub')
| -rw-r--r-- | library/SubcircuitLibrary/4012/4012.sub | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/4012/4012.sub b/library/SubcircuitLibrary/4012/4012.sub new file mode 100644 index 00000000..65263f03 --- /dev/null +++ b/library/SubcircuitLibrary/4012/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012 +.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4012
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