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author | Sumanto Kar | 2022-02-08 16:22:43 +0530 |
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committer | GitHub | 2022-02-08 16:22:43 +0530 |
commit | 536407d5e932bc3ba94b0286d1ee659205088520 (patch) | |
tree | 9f74c56f253ad28e98173e9486c2b956a252126b /library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib | |
parent | c28c426d72c72ef2327021f1fe8d7a7d97a76aa1 (diff) | |
parent | b2c5afc0a22390f221083af05c1ce2703907df25 (diff) | |
download | eSim-536407d5e932bc3ba94b0286d1ee659205088520.tar.gz eSim-536407d5e932bc3ba94b0286d1ee659205088520.tar.bz2 eSim-536407d5e932bc3ba94b0286d1ee659205088520.zip |
Merge pull request #182 from Eyantra698Sumanto/master
Added Clock Generator and DAC
Diffstat (limited to 'library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib')
-rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib new file mode 100644 index 00000000..f7dfef8a --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# summer +# +DEF summer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "summer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN1 1 -400 150 200 R 50 50 1 1 I +X IN2 2 -400 -150 200 R 50 50 1 1 I +X OUT 3 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library |