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| author | Anjali Jaiswal | 2019-07-01 12:23:31 +0530 |
|---|---|---|
| committer | Sunil Shetye | 2019-07-01 12:23:31 +0530 |
| commit | 6b410587b3101af7c6378c8e816e7d357beb1929 (patch) | |
| tree | 4971a8a2a8c15397d83f59315b866a87b9faf9bc /code/subcircuit | |
| parent | 4540e4674cbf5c5986bbd0dd81a4d379207e8b3f (diff) | |
| download | eSim-6b410587b3101af7c6378c8e816e7d357beb1929.tar.gz eSim-6b410587b3101af7c6378c8e816e7d357beb1929.tar.bz2 eSim-6b410587b3101af7c6378c8e816e7d357beb1929.zip | |
Added missing .rst files. (#111)
* Added rst files
Diffstat (limited to 'code/subcircuit')
| -rw-r--r-- | code/subcircuit/uploadSub.rst | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/code/subcircuit/uploadSub.rst b/code/subcircuit/uploadSub.rst new file mode 100644 index 00000000..48a0db15 --- /dev/null +++ b/code/subcircuit/uploadSub.rst @@ -0,0 +1,5 @@ +Upload subcircuit component +=========================== + +.. automodule:: subcircuit.uploadSub + :members: |