initial commit

24 files changed, 1893 insertions, 0 deletions

diff --git a/Windows/spice/examples/xspice/analog_models1_transient.sp b/Windows/spice/examples/xspice/analog_models1_transient.sp
new file mode 100644
index 00000000..a74bd6ca
--- /dev/null
+++ b/Windows/spice/examples/xspice/analog_models1_transient.sp
@@ -0,0 +1,65 @@
+Code Model Test - Transient: gain, summer, mult, divide, pwl
+*
+*
+*** analysis type ***
+.control
+tran .1s 10s
+plot v(1) v(10) v(20) v(30) v(40) v(50)
+.endc
+*
+*** input sources ***
+*
+v1 1 0 DC PWL(0 0 10 10) 
+*
+v2 2 0 DC 2
+*
+*** gain block ***
+a1 1 10 gain1 
+.model gain1 gain (in_offset=0.0 gain=2.0 out_offset=0.0)
+*
+*
+*** summer block ***
+a2 [1 2] 20 summer1
+.model summer1 summer (in_offset=[0.0 0.0] in_gain=[1.0 1.0] 
++                      out_gain=1.0  out_offset=0.0)
+*
+*
+*** mult block ***
+a3 [1 1] 30 mult1
+.model mult1 mult (in_offset=[0.0 0.0] in_gain=[1.0 1.0] 
++                      out_gain=0.1  out_offset=0.0)
+*
+*
+*** divider block ***
+a4 2 1 40 divide1
+.model divide1 divide (num_offset=0.0 num_gain=1.0 den_offset=0.0 den_gain=1.0 
++                      den_lower_limit=0.1 den_domain=1.0e-16 
++                      fraction=false out_gain=1.0 out_offset=0.0)
+*
+*
+*** pwl block ***
+a5 1 50 pwl1
+.model pwl1 pwl (x_array=[-1.0 0.0 1.0 2.0 3.0 4.0 5.0]
++                y_array=[ 0.0 0.0 1.0 4.0 4.5 5.0 5.0]
++                input_domain=0.01 fraction=TRUE)
+*
+*
+*** resistors to ground ***
+r1 1 0 1k
+r2 2 0 1k
+r3 3 0 1k
+*
+r10 10 0 1k
+r20 20 0 1k
+r30 30 0 1k
+r40 40 0 1k
+r50 50 0 1k
+*
+*
+.end
+
+
+
+
+
+
diff --git a/Windows/spice/examples/xspice/delta-sigma/README b/Windows/spice/examples/xspice/delta-sigma/README
new file mode 100644
index 00000000..3ce6ce63
--- /dev/null
+++ b/Windows/spice/examples/xspice/delta-sigma/README
@@ -0,0 +1,25 @@
+A simple delta sigma converter using XSPICE
+according to 
+Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+Fig. 2.13, p. 31; Fig. 2.27, p.58
+
+
+delta-sigma-1.cir
+converter complete, tested against sine input
+
+mod1-ct.cir
+first order modulator
+consists of analog continuous time integrator and
+digitally latched comparator
+
+count-latch-dac.cir
+contains subcircuits of 
+10 bit digital latch
+10 bit counter, non-revolving, saturating
+simple 10 bit DAC with analog B source
+
+mod1-ct-test.cir
+test of modulator with sine input, shows noise shaping 20dB/decade
+
+counter-test.cir
+simple test with reset
diff --git a/Windows/spice/examples/xspice/delta-sigma/count-latch-dac.cir b/Windows/spice/examples/xspice/delta-sigma/count-latch-dac.cir
new file mode 100644
index 00000000..7a8c7d90
--- /dev/null
+++ b/Windows/spice/examples/xspice/delta-sigma/count-latch-dac.cir
@@ -0,0 +1,81 @@
+* counter, latch DAC
+
+* 10 bit synchronous digital counter
+* inhibit at overflow, no revolving
+.subckt count10 din dinb dclk drs dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 
+
+* j k clk set reset out nout
+ajk1 din dinb diclk ds1 drs dout1 dnout1 jkflop
+ajk2 dout1 dout1 diclk ds2 drs dout2 dnout2 jkflop
+ajk3 djk3 djk3 diclk ds3 drs dout3 dnout3 jkflop
+ajk4 djk4 djk4 diclk ds4 drs dout4 dnout4 jkflop
+ajk5 djk5 djk5 diclk ds1 drs dout5 dnout5 jkflop
+ajk6 djk6 djk6 diclk ds2 drs dout6 dnout6 jkflop
+ajk7 djk7 djk7 diclk ds3 drs dout7 dnout8 jkflop
+ajk8 djk8 djk8 diclk ds4 drs dout8 dnout8 jkflop
+ajk9 djk9 djk9 diclk ds3 drs dout9 dnout9 jkflop
+ajk10 djk10 djk10 diclk ds4 drs dout10 dnout10 jkflop
+
+aand1 [dout1 dout2] djk3 and1
+aand2 [dout1 dout2 dout3] djk4 and1
+aand3 [dout1 dout2 dout3 dout4] djk5 and1
+aand4 [dout1 dout2 dout3 dout4 dout5] djk6 and1
+aand5 [dout1 dout2 dout3 dout4 dout5 dout6] djk7 and1
+aand6 [dout1 dout2 dout3 dout4 dout5 dout6 dout7] djk8 and1
+aand7 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8] djk9 and1
+aand8 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9] djk10 and1
+
+* inhibit revolving of counter, just let it saturate
+* (footnote p. 57)
+aand_all [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10] dinhibit nand1
+aandclk [dclk dinhibit] diclk and1
+
+
+.model nand1 d_nand(rise_delay = 1e-9 fall_delay = 1e-9
++ input_load = 0.5e-12)
+
+.model and1 d_and(rise_delay = 1e-9 fall_delay = 1e-9
++ input_load = 0.5e-12)
+
+.model jkflop d_jkff(clk_delay = 1.0e-9 set_delay = 1e-9
++ reset_delay = 1e-9 ic = 0 rise_delay = 1.0e-9
++ fall_delay = 1e-9)
+
+.ends count 10
+
+** 10 bit edge triggered latch
+.subckt latch10 din1 din2 din3 din4 din5 din6 din7 din8 din9 din10
++ dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 dclk
+
+*data clk set reset out nout
+aff1 din1 dclk dzero dzero dout1 dnout1 flop1
+aff2 din2 dclk dzero dzero dout2 dnout2 flop1
+aff3 din3 dclk dzero dzero dout3 dnout3 flop1
+aff4 din4 dclk dzero dzero dout4 dnout4 flop1
+aff5 din5 dclk dzero dzero dout5 dnout5 flop1
+aff6 din6 dclk dzero dzero dout6 dnout6 flop1
+aff7 din7 dclk dzero dzero dout7 dnout7 flop1
+aff8 din8 dclk dzero dzero dout8 dnout8 flop1
+aff9 din9 dclk dzero dzero dout9 dnout9 flop1
+aff10 din10 dclk dzero dzero dout10 dnout10 flop1
+
+.model flop1 d_dff(clk_delay = 1e-9 set_delay = 0
++ reset_delay = 0 ic = 0 rise_delay = 1e-9
++ fall_delay = 1e-9)
+
+.ends latch10
+
+** emulation of 10 bit DAC
+.subckt dac10  din1 din2 din3 din4 din5 din6 din7 din8 din9 din10 aout
+.param vref=1
+abridge1 [din1 din2 din3 din4 din5 din6 din7 din8 din9 din10] 
++ [ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10] dac1
+BVout aout 0 V = 'vref'*(v(ain10)/2 + v(ain9)/4 + v(ain8)/8 + v(ain7)/16 + v(ain6)/32 +
++ v(ain5)/64 + v(ain4)/128 + v(ain3)/256 + v(ain2)/512 + v(ain1)/1024)
+
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-9
++ t_fall = 1e-9)
+
+.ends dac10
+
diff --git a/Windows/spice/examples/xspice/delta-sigma/counter-test.cir b/Windows/spice/examples/xspice/delta-sigma/counter-test.cir
new file mode 100644
index 00000000..8bf2baf6
--- /dev/null
+++ b/Windows/spice/examples/xspice/delta-sigma/counter-test.cir
@@ -0,0 +1,42 @@
+* 10 bit synchronous digital counter
+* inhibit at overflow, no revolving
+* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+* Fig. 2.27, p. 58
+
+* clock generation
+* PULSE(V1 V2 TD TR TF PW PER)
+vclk aclk 0 dc 0 pulse(0 1 1u 2n 2n 1u 2u)
+
+* reset generation
+* single pulse, actual value stored in latch and read by DAC
+vres ars 0 dc 0 pulse(0 1 1.1m 2n 2n 1u 2.2m)
+
+vone aone 0 dc 1
+vzero azero 0 dc 0
+
+* digital one
+* digital zero
+abridge1 [aone azero] [done dzero] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+* digital clock
+* digital reset
+abridge2 [aclk ars] [dclk dreset] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+XCounter done done dclk dreset dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10
+Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 dreset
++ latch10
+Xdac dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adacout dac10 
+
+.include count-latch-dac.cir
+
+.control
+tran 1u 2.5m
+eprint dout1 dout2 dout3 dout4  dout5 dout6 dout7 dout8 dout9 dout10 > digi4b.txt
+eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 >> digi4b.txt
+plot adacout
+.endc
+
+.end
diff --git a/Windows/spice/examples/xspice/delta-sigma/delta-sigma-1.cir b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-1.cir
new file mode 100644
index 00000000..08322260
--- /dev/null
+++ b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-1.cir
@@ -0,0 +1,106 @@
+* delta sigma A/D converter 9 bit
+* first-order continuous time delta sigma modulator
+* sinc filter with counter
+* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+* Fig. 2.13, p. 31; Fig. 2.27, p.58
+
+** sine input signal parameters
+.param infreq=500 inampl=0.5
+** clock
+.param clkfreq=5Meg
+** simulation time
+.param simtime = 2m
+.csparam simtime = 'simtime'
+** sample clock cycles
+.param samples=500
+
+.global dzero done
+
+** input signal
+* SIN(VO VA FREQ TD THETA)
+vin inp inm dc 0 sin(0 'inampl' 'infreq' 0 0)
+* steps from -0.5 to 0.4
+*vin inp inm dc 0 pwl(0 -0.5 0.2m -0.5 0.201m -0.4 0.4m -0.4 0.401m -0.3 0.6m -0.3
+*+  0.601m -0.2 0.8m -0.2  0.801m -0.1 1.0m -0.1  1.001m 0.0 1.2m 0.0  1.201m 0.1 1.4m 0.1 
+*+  1.401m 0.2 1.6m 0.2 1.601m 0.3 1.8m 0.3 1.801m 0.4 2m 0.4)
+
+** clock and constant logic levels
+* PULSE(V1 V2 TD TR TF PW PER)
+vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq')
+
+* digital one
+* digital zero
+vone aone 0 dc 1
+vzero azero 0 dc 0
+abridge1 [aone azero] [done dzero] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+* digital clock
+abridge2 [aclk] [dclk] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+****** delta-sigma converter****************************************************************
+* modulator
+* inp inm: analog in + -
+* dclk digital clock in
+* dv, dvb: modulator non-inverting/inverting out
+Xmod inp inm dclk dv dvb mod1
+* sinc filter, decimator
+* dlout1 ..dlout10: converter 10 bit digital out
+xsinc dv dvb dclk  dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 sinc1
+********************************************************************************************
+
+** DACs for measuring and plotting
+* converter output
+Xdac_latch dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adaclout dac10 
+* counter inside of sinc filter
+Xdac_counter xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5
++ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 adaccout dac10
+
+* load modulator mod1 subcircuit
+.include mod1-ct.cir
+
+* load counter, d-latch and 10 bit DAC
+.include count-latch-dac.cir
+
+** sinc filter 1st order subcircuit
+.subckt sinc1 din dinb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10
+XCounter din dinb dclk ddivndel2 dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10
+Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 ddivndel1
++ latch10
+
+* digital divider dclk/samples
+adivn dclk ddivn divider
+.model divider d_fdiv(div_factor = 'samples' high_cycles = 1
++ i_count = 0 rise_delay = 1e-9 fall_delay = 1e-9)
+
+* clock delays
+adelay ddivn ddivndel1 buff1 ; set latch
+adelay2 ddivndel1 ddivndel2 buff1 ; reset counter
+.model buff1 d_buffer(rise_delay = '1/clkfreq/8' fall_delay = '1/clkfreq/8'
++ input_load = 0.5e-12)
+
+.ends sinc1
+
+** for plotting
+abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac1
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-9
++ t_fall = 1e-9)
+
+
+.control
+save inp inm adaclout adaccout ; save memory space
+tran 0.1u $&simtime
+* analog out, scaled 'manually'; sinc filter counter; analog differential in
+plot 4.1*(adaclout-0.486) adaccout v(inp)-v(inm) ylimit -0.6 0.6
+* modulator dig out
+* eprint dv > digi1.txt
+* 
+*eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 
+*+ xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5
+*+ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 > digi4b.txt
+.endc
+
+.end
diff --git a/Windows/spice/examples/xspice/delta-sigma/delta-sigma-oc.cir b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-oc.cir
new file mode 100644
index 00000000..a0418197
--- /dev/null
+++ b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-oc.cir
@@ -0,0 +1,95 @@
+* delta sigma A/D converter 9 bit
+* first-order continuous time delta sigma modulator
+* sinc filter with counter
+* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+* Fig. 2.13, p. 31; Fig. 2.27, p.58
+
+** sine input signal parameters
+.param infreq=500 inampl=0.5
+** clock
+.param clkfreq=5Meg
+** simulation time
+.param simtime = 2m
+.csparam simtime = 'simtime'
+** sample clock cycles
+.param samples=500
+
+.global dzero done
+
+** input signal
+* SIN(VO VA FREQ TD THETA)
+vin inp inm dc 0 sin(0 'inampl' 'infreq' 0 0)
+* steps from -0.5 to 0.4
+*vin inp inm dc 0 pwl(0 -0.5 0.2m -0.5 0.201m -0.4 0.4m -0.4 0.401m -0.3 0.6m -0.3
+*+  0.601m -0.2 0.8m -0.2  0.801m -0.1 1.0m -0.1  1.001m 0.0 1.2m 0.0  1.201m 0.1 1.4m 0.1 
+*+  1.401m 0.2 1.6m 0.2 1.601m 0.3 1.8m 0.3 1.801m 0.4 2m 0.4)
+
+** clock and constant logic levels
+* PULSE(V1 V2 TD TR TF PW PER)
+vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq')
+
+* digital one
+* digital zero
+vone aone 0 dc 1
+vzero azero 0 dc 0
+abridge1 [aone azero] [done dzero] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+* digital clock
+abridge2 [aclk] [dclk] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+****** delta-sigma converter****************************************************************
+* modulator
+* inp inm: analog in + -
+* dclk digital clock in
+* dv, dvb: modulator non-inverting/inverting out
+Xmod inp inm dclk dv dvb mod1
+* sinc filter, decimator
+* dlout1 ..dlout10: converter 10 bit digital out
+xsinc dv dvb dclk  dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 sinc1
+********************************************************************************************
+
+** DACs for measuring and plotting
+* converter output
+Xdac_latch dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adaclout dac10 
+* counter inside of sinc filter
+Xdac_counter xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5
++ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 adaccout dac10
+
+* load modulator mod1 subcircuit
+.include mod1-ct.cir
+
+* load counter, d-latch and 10 bit DAC
+.include count-latch-dac.cir
+
+** sinc filter 1st order subcircuit
+.subckt sinc1 din dinb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10
+XCounter din dinb dclk ddivndel2 dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10
+Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 ddivndel1
++ latch10
+
+* digital divider dclk/samples
+adivn dclk ddivn divider
+.model divider d_fdiv(div_factor = 'samples' high_cycles = 1
++ i_count = 0 rise_delay = 1e-9 fall_delay = 1e-9)
+
+* clock delays
+adelay ddivn ddivndel1 buff1 ; set latch
+adelay2 ddivndel1 ddivndel2 buff1 ; reset counter
+.model buff1 d_buffer(rise_delay = '1/clkfreq/8' fall_delay = '1/clkfreq/8'
++ input_load = 0.5e-12)
+
+.ends sinc1
+
+** for plotting
+abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac1
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-9
++ t_fall = 1e-9)
+
+.save inp inm adaclout adaccout ; save memory space
+.tran 0.1u 2m
+
+.end
diff --git a/Windows/spice/examples/xspice/delta-sigma/mod1-ct-test.cir b/Windows/spice/examples/xspice/delta-sigma/mod1-ct-test.cir
new file mode 100644
index 00000000..7ce7b0d3
--- /dev/null
+++ b/Windows/spice/examples/xspice/delta-sigma/mod1-ct-test.cir
@@ -0,0 +1,52 @@
+* first-order delta sigma modulator
+* continuous time
+* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+* Fig. 2.13, p. 31
+
+** signal
+.param infreq=13k inampl=0.3
+** clock
+.param clkfreq=5Meg
+** simulation time
+.param simtime = 5m
+.csparam simtime = 'simtime'
+
+** input signal
+*SIN(VO VA FREQ TD THETA)
+vin in+ in- dc 0 sin(0 'inampl' 'infreq' 0 0)
+
+* clock generation
+* PULSE(V1 V2 TD TR TF PW PER)
+vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq')
+
+* digital one
+* digital zero
+vone aone 0 dc 1
+vzero azero 0 dc 0
+abridge1 [aone azero] [done dzero] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+* digital clock
+abridge2 [aclk] [dclk] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+Xmod in+ in- dclk dv dvb mod1
+
+* load mod1 subcircuit
+.include mod1-ct.cir
+
+.control
+save xmod.adffq in+ in- xmod.outintp xmod.outintn
+tran 0.01u $&simtime
+* digit density vs input
+plot xmod.adffq "v(in+) - v(in-)" xlimit 0.1m 0.2m
+* modulator integrator out, digital out
+plot xmod.outintp-xmod.outintn xmod.adffq xlimit 0.140m 0.148m
+*eprint dv dclk > digi1.txt
+linearize xmod.adffq
+fft xmod.adffq
+* noise shaping 20dB/decade
+plot db(xmod.adffq) xlimit 10k 1Meg xlog ylimit -20 -120
+.endc
+
+.end
diff --git a/Windows/spice/examples/xspice/delta-sigma/mod1-ct.cir b/Windows/spice/examples/xspice/delta-sigma/mod1-ct.cir
new file mode 100644
index 00000000..bf3129b7
--- /dev/null
+++ b/Windows/spice/examples/xspice/delta-sigma/mod1-ct.cir
@@ -0,0 +1,46 @@
+* delta sigma modulator 
+* first order, continuous time
+
+.subckt mod1 ainp ainn dclk ddffq ddffqb
+* integrator and summer
+Ri1 ainn inintn 500
+Rf1 adffq inintn 500
+Cint1 outintp inintn 1n
+.IC v(outintp) = 0 v(inintp) = 0
+*
+Rshunt1 outintp 0 100Meg
+Rshunt2 initn 0 100Meg
+*
+Ri2 ainp inintp 500
+Rf2 adffqb inintp 500
+Cint2 outintn inintp 1n
+.IC v(outintn) = 0 v(inintn) = 0
+*
+Rshunt3 outintn 0 100Meg
+Rshunt4 inintp 0 100Meg
+*
+aint %vd(inintp inintn) %vd(outintp outintn) amp
+.model amp gain ( in_offset =0.0 gain =100000
++ out_offset = 0)
+
+* latched comparator (code model or B source, analog in, digital out)
+*acomp %vd(outintp outintn) acompout limit5
+*.model limit5 limit(in_offset=0 gain=100000 out_lower_limit=-1.0
+*+ out_upper_limit=1.0 limit_range=0.10 fraction=FALSE)
+*
+BComp acompout 0 V = (V(outintp) - V(outintn)) >= 0 ? 1 : -1
+*
+abridge2 [acompout] [dcompout] adc_buff
+.model adc_buff adc_bridge(in_low = 0 in_high = 0)
+*
+* D flip flop: data clk set reset out nout
+adff1 dcompout dclk ds drs ddffq ddffqb flop2
+.model flop2 d_dff(clk_delay = 1e-9 set_delay = 1.0e-9
++ reset_delay = 1.0e-9 ic = 0 rise_delay = 1.0e-9
++ fall_delay = 1e-9)
+
+abridge1 [ddffq ddffqb dclk] [adffq adffqb aclk] dac1
+.model dac1 dac_bridge(out_low = -1 out_high = 1 out_undef = 0
++ input_load = 5.0e-12
+
+.ends mod1
diff --git a/Windows/spice/examples/xspice/fstest.sp b/Windows/spice/examples/xspice/fstest.sp
new file mode 100644
index 00000000..f0f552a8
--- /dev/null
+++ b/Windows/spice/examples/xspice/fstest.sp
@@ -0,0 +1,26 @@
+* filesource Test
+
+* two differential ports 1 0 and 3 0 are used, so your input file
+* has to have three columns (time, port_value 1, portvalue 2)
+
+AFILESRC %vd([1 0 3 0]) filesrc
+.model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1] timerelative=false amplstep=false)
+
+V2 2 0 0.0 SIN(0 1 1MEG 0 0 0.0)
+V4 4 0 0.0 SIN(0 1 1MEG 0 0 90.0)
+
+.tran 1n 1.0u
+
+.control
+run
+*listing param
+wrdata vspice V(1) V(2) V(3) V(4)
+
+
+plot V(1) V(2) V(3) V(4)
+
+* error between interpolation and sine source
+* should be less than 1mV up to 1us
+plot V(1,2) V(3,4)
+.endc
+.end
diff --git a/Windows/spice/examples/xspice/pll/README b/Windows/spice/examples/xspice/pll/README
new file mode 100644
index 00000000..f5c38b39
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/README
@@ -0,0 +1,39 @@
+This directory contains a mixed mode pll, combining
+ngspice and XSPICE circuit blocks.
+The pll consists of the following blocks:
+
+** voltage controlled oscillator:
+vco_sub.cir
+   7 stage ring oscillator with gain cells, CMOS devices
+or
+vco_sub_new.cir
+   vco made from code model d_osc, cntl_array/freq_array data
+   are gained by running test-vco.cir with vco_sub.cir
+
+** digital divider and frequency reference:
+pll-xspice.cir
+
+** phase frequency detector:
+f-p-det-d-sub.cir
+
+** loop filter:
+loop-filter.cir
+   switched current sources as charge pump, 2nd order
+   passive RC filter
+or
+loop-filter-2.cir
+   transistors as switches for charge pump, 2nd or 3rd
+   order passive RC filters
+
+** main simulation control:
+pll-xspice.cir
+
+Two test files are included:
+test-vco.cir simulates vco frequency versus control voltage
+test-f-p-det.cir simulates the phase frequency detector and the loop filter.
+
+The main building blocks are organised as subcircuits.
+
+main simulation control with three reference frequencies:
+pll-xspice-fstep.cir
+   simulates two steps of the reference in one simulation run
diff --git a/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir b/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir
new file mode 100644
index 00000000..cdd5af9e
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir
@@ -0,0 +1,16 @@
+* frequency-phase detector according to
+* http://www.uwe-kerwien.de/pll/pll-phasenvergleich.htm
+
+.subckt f-p-det d_R d_V d_U d_U_ d_D d_D_
+
+aa1 [d_U d_D] d_rset and1
+.model and1 d_and(rise_delay = 1e-10 fall_delay = 0.1e-9
++ input_load = 0.5e-12)
+
+ad1 d_d1 d_R d_d0 d_rset d_U d_U_ flop1
+ad2 d_d1 d_V d_d0 d_rset d_D d_D_ flop1
+.model flop1 d_dff(clk_delay = 1.0e-10 set_delay = 1.0e-10
++ reset_delay = 1.0e-10 ic = 2 rise_delay = 1.0e-10
++ fall_delay = 1e-10)
+
+.ends f-p-det
diff --git a/Windows/spice/examples/xspice/pll/loop-filter-2.cir b/Windows/spice/examples/xspice/pll/loop-filter-2.cir
new file mode 100644
index 00000000..3d093167
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/loop-filter-2.cir
@@ -0,0 +1,50 @@
+* loop filter for pll
+* in: d_up d_down digital data
+* out: vout, vco control voltage
+* using transistors to switch current
+* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm
+* digital input d_Un d_D
+* anlog output vout
+
+
+.subckt loopf d_Un d_D vout
+
+.param initcond=2.5
+
+vdd dd 0 dc 'vcc'
+vss ss 0 dc 0
+
+* "driver" circuit, digital in, analog out
+abridge-f1 [d_Un d_D] [u1n d1] dac1
+.model dac1 dac_bridge(out_low = 0 out_high = 'vcc' out_undef = 'vcc/2'
++ input_load = 5.0e-12 t_rise = 1e-10
++ t_fall = 1e-10)
+
+* uses BSIM3 model parameters from pll-xspice_2.cir
+* transistors as switches
+mnd  dra d1  ss  ss  n1  w=12u  l=0.35u  AS=24p AD=24p PS=28u PD=28u
+mpd  dra u1n  dd  dd  p1  w=24u l=0.35u  AS=48p AD=48p PS=52u PD=52u
+
+*** passive filter elements ***
+*third order filter
+*parameters absolutely _not_ optimised
+*better check
+* http://www.national.com/assets/en/boards/deansbook4.pdf
+*to do so
+.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(int1)='initcond' v(u1n)='vcc' v(d1)=0
+R1 dra int1 300
+R2 int1 c1 200
+C1 c1 0 10n
+C2 int1 0 5n
+R3 int1 vout 50
+C3 vout 0 0.5n
+
+*second order filter
+*parameters not optimized
+*.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(u1n)='vcc' v(d1)=0
+*R1 dra vout 300
+*R2 vout c1 200
+*C1 c1 0 10n
+*C2 vout 0 5n
+
+.ends loopf
diff --git a/Windows/spice/examples/xspice/pll/loop-filter.cir b/Windows/spice/examples/xspice/pll/loop-filter.cir
new file mode 100644
index 00000000..a83ebb7a
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/loop-filter.cir
@@ -0,0 +1,31 @@
+* loop filter for pll
+* in: d_up d_down digital data
+* out: vout, vco control voltage
+* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm
+
+.subckt loopfe d_U d_D vout
+
+.param loadcur=5m
+.param initcond=2.5
+
+v1 vtop 0 1
+v2 vbot 0 -1
+
+abridge-f1 [d_U d_D] [u1 d1] dac1
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-10
++ t_fall = 1e-10)
+
+*top switched current source
+Gtop vtop vout cur='loadcur*v(u1)'
+*bottom switched current source
+Gbot vout vbot cur='loadcur*v(d1)'
+
+*passive filter elements
+.ic v(vout)='initcond' v(c1)='initcond'
+R2 vout c1 200
+C1 c1 0 5n
+C2 vout 0 5n
+Rshunt vout 0 10000k
+
+.ends
diff --git a/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir b/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir
new file mode 100644
index 00000000..5c79e152
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir
@@ -0,0 +1,165 @@
+* pll circuit using xspice code models
+* three frequencies generate steps in control voltage v(cont)
+
+.param vcc=3.3
+.param divisor=40
+.param fref=10e6
+.param fref2=9e6
+.param fref3=11e6
+.csparam simtime=45u
+.csparam f2='fref2'
+.csparam f3='fref3'
+
+* digital zero and one
+.global d_d0 d_d1
+
+vdd dd 0 dc 'vcc'
+
+* 10 MHz reference frequency
+* PULSE(V1 V2 TD TR TF PW PER)
+vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n  '1/fref/2' '1/fref')
+abridgeref [ref] [d_ref] adc_vbuf
+.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5)
+
+*digital zero
+vzero z 0 dc 0
+abridgev3 [z] [d_d0] adc_vbuf
+.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
+*digital one
+ainv1 d_d0 d_d1 invd1
+.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
+
+* vco
+* buf: analog out
+* d_digout: digital out
+* cont: analog control voltage
+* dd: analog supply voltage
+*.include vco_sub.cir
+*xvco buf d_digout cont dd ro_vco
+.include vco_sub_new.cir
+xvco buf d_digout cont dd d_osc_vco 
+
+* digital divider
+adiv1 d_digout d_divout divider
+.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2'
++ i_count = 4 rise_delay = 1e-10
++ fall_delay = 1e-10)
+
+* frequency phase detector
+.include f-p-det-d-sub.cir
+Xfpdet d_divout d_ref d_U d_Un d_D d_Dn  f-p-det
+
+* loop filter
+*2nd or 3rd order, transistors as switches
+.include loop-filter-2.cir
+Xlf d_Un d_D cont loopf
+* 2nd order, Exxxx voltage controlled current sources as 'switches'
+* loop filter current sources as charge pump
+*.include loop-filter.cir
+*Xlf d_U d_D cont loopfe
+
+* d to a for plotting
+abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1 d1] dac1 ; change to d_u or d_Un
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-10
++ t_fall = 1e-10)
+
+.control
+save cont s1 s2 u1 d1
+iplot cont
+* calculate breakpoint for switching frequency
+let t1_3 = simtime/3
+set ti1_3 ="$&t1_3"
+let t2_3 = simtime/3*2
+set ti2_3 ="$&t2_3"
+stop when time=$ti1_3
+stop when time=$ti2_3
+* calculate new periods for f2
+let per2=1/f2
+let pw2 = per2/2
+let per3=1/f3
+let pw3 = per3/2
+*simulate
+tran 0.1n $&simtime uic
+*change frequency after stopping
+* first pair of [] without spaces, second pair with spaces
+alter @vref[pulse] = [ 0 3.3 10n 1n 1n  $&pw2 $&per2 ]
+resume
+*another change after second stop
+alter @vref[pulse] = [ 0 3.3 10n 1n 1n  $&pw3 $&per3 ]
+resume
+rusage
+plot cont s1 s2+1.2 u1+2.4 d1+3.6 xlimit 15u 16u
+*plot cont
+.endc
+
+*model = bsim3v3
+*Berkeley Spice Compatibility 
+* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
+.model N1 NMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=9.36e-8 Wint=1.47e-7
++Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612 
++Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2 
++Nlx= 3.52291E-08  W0= 1.163e-6 
++K3b= 2.233 
++Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11 
++Rdsw= 650  U0= 388.3203 wr=1
++A0= .3496967 Ags=.1    B0=0.546    B1= 1   
++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
++Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9 
++Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04 
++Cdsc=-2.147181E-05   
++Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0 
++ Cdscd =  0 Prwg =  0 
++Eta0= 1.0281729E-02  Etab=-5.042203E-03 
++Dsub= .31871233 
++Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03 
++Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
++Pvag= 0 delta=0.01
++ Wl =  0 Ww = -1.420242E-09 Wwl =  0 
++ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10 
++ Lw =  0 Lwl =  0 Lln =  .316394 
++ Lwn =  0
++kt1=-.3  kt2=-.051 
++At= 22400 
++Ute=-1.48 
++Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10 
++Kt1l=0 Prt=764.3
+
+.model P1 PMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=6.23e-8 Wint=1.22e-7
++Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82 
++Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677 
++Nlx= 1.28e-8  W0= 2.1e-6 
++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 
++Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11 
++ Rdsw= 460  U0= 138.7609 
++A0= .4716551 Ags=0.12 
++Keta=-1.871516E-03  A1= .3417965  A2= 0.83 
++Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03 
++Cdsc= 8.937517E-04 
++Cdscb= 1.45e-4  Cdscd=1.04e-4
++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
++Eta0= 6.024776E-02  Etab=-4.64593E-03 
++Dsub= .23222404 
++Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3 
++Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09 
++Pvag= 0 
++kt1= -0.25  kt2= -0.032 prt=64.5 
++At= 33000 
++Ute= -1.5 
++Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0 
++Kt1l=0
+
+
+.end
diff --git a/Windows/spice/examples/xspice/pll/pll-xspice.cir b/Windows/spice/examples/xspice/pll/pll-xspice.cir
new file mode 100644
index 00000000..1d14368d
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/pll-xspice.cir
@@ -0,0 +1,144 @@
+* pll circuit using xspice code models
+* output frequency 400 MHz
+* locked to a 1 or 10 MHz reference
+
+.param vcc=3.3
+.param divisor=40
+.param fref=10e6
+.csparam simtime=25u
+
+.global d_d0 d_d1
+
+vdd dd 0 dc 'vcc'
+*vco cont 0 dc 1.9
+
+*PULSE(V1 V2 TD TR TF PW PER)
+* reference frequency selected by param fref
+* PULSE(V1 V2 TD TR TF PW PER)
+vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n  '1/fref/2' '1/fref')
+abridgeref [ref] [d_ref] adc_vbuf
+.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5)
+
+*digital zero
+vzero z 0 dc 0
+abridgev3 [z] [d_d0] adc_vbuf
+.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
+*digital one
+ainv1 d_d0 d_d1 invd1
+.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
+
+* vco
+* buf: analog out
+* d_digout: digital out
+* cont: analog control voltage
+* dd: analog supply voltage
+*.include vco_sub.cir
+*xvco buf d_digout cont dd ro_vco
+.include vco_sub_new.cir
+xvco buf d_digout cont dd d_osc_vco 
+
+* digital divider
+adiv1 d_digout d_divout divider
+.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2'
++ i_count = 4 rise_delay = 1e-10
++ fall_delay = 1e-10)
+
+* frequency phase detector
+.include f-p-det-d-sub.cir
+Xfpdet d_divout d_ref d_U d_Un d_D d_Dn  f-p-det
+
+* loop filters
+*2nd or 3rd order, transistors as switches
+.include loop-filter-2.cir
+Xlf d_Un d_D cont loopf
+* 2nd order, Exxxx voltage controlled current sources as 'switches'
+* loop filter current sources as charge pump
+*.include loop-filter.cir
+*Xlf d_U d_D cont loopfe
+
+* d to a for plotting
+abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-10
++ t_fall = 1e-10)
+
+.control
+save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory
+iplot cont
+tran 0.1n $&simtime uic
+rusage
+plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u
+plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m
+*plot cont
+.endc
+
+*model = bsim3v3
+*Berkeley Spice Compatibility 
+* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
+.model N1 NMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=9.36e-8 Wint=1.47e-7
++Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612 
++Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2 
++Nlx= 3.52291E-08  W0= 1.163e-6 
++K3b= 2.233 
++Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11 
++Rdsw= 650  U0= 388.3203 wr=1
++A0= .3496967 Ags=.1    B0=0.546    B1= 1   
++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
++Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9 
++Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04 
++Cdsc=-2.147181E-05   
++Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0 
++ Cdscd =  0 Prwg =  0 
++Eta0= 1.0281729E-02  Etab=-5.042203E-03 
++Dsub= .31871233 
++Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03 
++Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
++Pvag= 0 delta=0.01
++ Wl =  0 Ww = -1.420242E-09 Wwl =  0 
++ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10 
++ Lw =  0 Lwl =  0 Lln =  .316394 
++ Lwn =  0
++kt1=-.3  kt2=-.051 
++At= 22400 
++Ute=-1.48 
++Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10 
++Kt1l=0 Prt=764.3
+
+.model P1 PMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=6.23e-8 Wint=1.22e-7
++Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82 
++Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677 
++Nlx= 1.28e-8  W0= 2.1e-6 
++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 
++Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11 
++ Rdsw= 460  U0= 138.7609 
++A0= .4716551 Ags=0.12 
++Keta=-1.871516E-03  A1= .3417965  A2= 0.83 
++Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03 
++Cdsc= 8.937517E-04 
++Cdscb= 1.45e-4  Cdscd=1.04e-4
++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
++Eta0= 6.024776E-02  Etab=-4.64593E-03 
++Dsub= .23222404 
++Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3 
++Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09 
++Pvag= 0 
++kt1= -0.25  kt2= -0.032 prt=64.5 
++At= 33000 
++Ute= -1.5 
++Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0 
++Kt1l=0
+
+
+.end
diff --git a/Windows/spice/examples/xspice/pll/pll-xspice_oc.cir b/Windows/spice/examples/xspice/pll/pll-xspice_oc.cir
new file mode 100644
index 00000000..f2d235c3
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/pll-xspice_oc.cir
@@ -0,0 +1,142 @@
+* pll circuit using xspice code models
+* output frequency 400 MHz
+* locked to a 1 or 10 MHz reference
+
+.param vcc=3.3
+.param divisor=40
+.param fref=10e6
+.csparam simtime=25u
+
+.control
+pre_unset ngdebug
+set noinit
+.endc
+
+.global d_d0 d_d1
+
+vdd dd 0 dc 'vcc'
+*vco cont 0 dc 1.9
+
+*PULSE(V1 V2 TD TR TF PW PER)
+* reference frequency selected by param fref
+* PULSE(V1 V2 TD TR TF PW PER)
+vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n  '1/fref/2' '1/fref')
+abridgeref [ref] [d_ref] adc_vbuf
+.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5)
+
+*digital zero
+vzero z 0 dc 0
+abridgev3 [z] [d_d0] adc_vbuf
+.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
+*digital one
+ainv1 d_d0 d_d1 invd1
+.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
+
+* vco
+* buf: analog out
+* d_digout: digital out
+* cont: analog control voltage
+* dd: analog supply voltage
+*.include vco_sub.cir
+*xvco buf d_digout cont dd ro_vco
+.include vco_sub_new.cir
+xvco buf d_digout cont dd d_osc_vco 
+
+* digital divider
+adiv1 d_digout d_divout divider
+.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2'
++ i_count = 4 rise_delay = 1e-10
++ fall_delay = 1e-10)
+
+* frequency phase detector
+.include f-p-det-d-sub.cir
+Xfpdet d_divout d_ref d_U d_Un d_D d_Dn  f-p-det
+
+* loop filters
+*2nd or 3rd order, transistors as switches
+.include loop-filter-2.cir
+Xlf d_Un d_D cont loopf
+* 2nd order, Exxxx voltage controlled current sources as 'switches'
+* loop filter current sources as charge pump
+*.include loop-filter.cir
+*Xlf d_U d_D cont loopfe
+
+* d to a for plotting
+abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-10
++ t_fall = 1e-10)
+
+.save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory
+.tran 0.1n 10u uic
+
+*model = bsim3v3
+*Berkeley Spice Compatibility 
+* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
+.model N1 NMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=9.36e-8 Wint=1.47e-7
++Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612 
++Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2 
++Nlx= 3.52291E-08  W0= 1.163e-6 
++K3b= 2.233 
++Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11 
++Rdsw= 650  U0= 388.3203 wr=1
++A0= .3496967 Ags=.1    B0=0.546    B1= 1   
++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
++Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9 
++Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04 
++Cdsc=-2.147181E-05   
++Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0 
++ Cdscd =  0 Prwg =  0 
++Eta0= 1.0281729E-02  Etab=-5.042203E-03 
++Dsub= .31871233 
++Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03 
++Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
++Pvag= 0 delta=0.01
++ Wl =  0 Ww = -1.420242E-09 Wwl =  0 
++ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10 
++ Lw =  0 Lwl =  0 Lln =  .316394 
++ Lwn =  0
++kt1=-.3  kt2=-.051 
++At= 22400 
++Ute=-1.48 
++Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10 
++Kt1l=0 Prt=764.3
+
+.model P1 PMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=6.23e-8 Wint=1.22e-7
++Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82 
++Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677 
++Nlx= 1.28e-8  W0= 2.1e-6 
++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 
++Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11 
++ Rdsw= 460  U0= 138.7609 
++A0= .4716551 Ags=0.12 
++Keta=-1.871516E-03  A1= .3417965  A2= 0.83 
++Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03 
++Cdsc= 8.937517E-04 
++Cdscb= 1.45e-4  Cdscd=1.04e-4
++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
++Eta0= 6.024776E-02  Etab=-4.64593E-03 
++Dsub= .23222404 
++Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3 
++Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09 
++Pvag= 0 
++kt1= -0.25  kt2= -0.032 prt=64.5 
++At= 33000 
++Ute= -1.5 
++Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0 
++Kt1l=0
+
+
+.end
diff --git a/Windows/spice/examples/xspice/pll/test-f-p-det.cir b/Windows/spice/examples/xspice/pll/test-f-p-det.cir
new file mode 100644
index 00000000..16060b9b
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/test-f-p-det.cir
@@ -0,0 +1,114 @@
+* test frequency-phase detector similar to 12040
+
+.param vcc=3.3
+.global d_d0 d_d1
+
+*PULSE(V1 V2 TD TR TF PW PER)
+v1 1 0 dc 0 pulse(0 'vcc' 10n 1n 1n 10n 20n)
+v2 2 0 dc 0 pulse(0 'vcc' 8n 1n 1n 10n 20n)
+
+*digital zero
+v3 3 0 dc 0
+abridgev1 [1 2 3] [d_sig1 d_sig2 d_d0] adc_vbuf
+.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
+*digital one
+ainv1 d_d0 d_d1 invd1
+.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
+
+Xfpdet d_sig1 d_sig2 d_U d_Un d_D d_Dn  f-p-det
+
+*.include f-p-det-sub.cir
+.include f-p-det-d-sub.cir
+
+* d to a for plotting
+abridge-w1 [d_sig1 d_sig2 d_U d_D] [s1 s2 u1 d1] dac1
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-10
++ t_fall = 1e-10)
+
+* loop filters
+*2nd or 3rd order, transistors as switches
+.include loop-filter-2.cir
+Xlf d_Un d_D cont loopf
+* 2nd order, Exxxx voltage controlled current sources as 'switches'
+* loop filter current sources as charge pump
+*.include loop-filter.cir
+*Xlf d_U d_D cont loopfe
+
+.control
+set xtrtol=2
+tran 0.1n 1000n
+plot s1 s2+1.2 u1+2.4 d1+3.6 xlimit 140n 200n
+.endc
+
+
+*model = bsim3v3
+*Berkeley Spice Compatibility
+* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
+.model N1 NMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8
++Tnom=27.0
++Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=9.36e-8 Wint=1.47e-7
++Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612
++Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2
++Nlx= 3.52291E-08  W0= 1.163e-6
++K3b= 2.233
++Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11
++Rdsw= 650  U0= 388.3203 wr=1
++A0= .3496967 Ags=.1    B0=0.546    B1= 1
++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
++Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9
++Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04
++Cdsc=-2.147181E-05
++Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0
++ Cdscd =  0 Prwg =  0
++Eta0= 1.0281729E-02  Etab=-5.042203E-03
++Dsub= .31871233
++Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03
++Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
++Pvag= 0 delta=0.01
++ Wl =  0 Ww = -1.420242E-09 Wwl =  0
++ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10
++ Lw =  0 Lwl =  0 Lln =  .316394
++ Lwn =  0
++kt1=-.3  kt2=-.051
++At= 22400
++Ute=-1.48
++Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10
++Kt1l=0 Prt=764.3
+
+.model P1 PMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8
++Tnom=27.0
++Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=6.23e-8 Wint=1.22e-7
++Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82
++Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677
++Nlx= 1.28e-8  W0= 2.1e-6
++K3b= -0.24 Prwg=-0.001 Prwb=-0.323
++Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11
++ Rdsw= 460  U0= 138.7609
++A0= .4716551 Ags=0.12
++Keta=-1.871516E-03  A1= .3417965  A2= 0.83
++Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03
++Cdsc= 8.937517E-04
++Cdscb= 1.45e-4  Cdscd=1.04e-4
++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
++Eta0= 6.024776E-02  Etab=-4.64593E-03
++Dsub= .23222404
++Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3
++Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09
++Pvag= 0
++kt1= -0.25  kt2= -0.032 prt=64.5
++At= 33000
++Ute= -1.5
++Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0
++Kt1l=0
+
+
+.end
diff --git a/Windows/spice/examples/xspice/pll/test_vco.cir b/Windows/spice/examples/xspice/pll/test_vco.cir
new file mode 100644
index 00000000..522eac00
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/test_vco.cir
@@ -0,0 +1,158 @@
+* Test of VCO: frequency versus control voltage
+* 7 stage Ring-Osc. made of gain cells BSIM3
+* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495
+* alternatively use d_osc code model
+* measure frequency of R.O. by fft 
+
+.param vcc=3.3
+.csparam simtime=500n
+
+vdd dd 0 dc 'vcc'
+vco cont 0 dc 2.5
+
+* vco
+* buf: analog out
+* d_digout: digital out
+* cont: analog control voltage
+* dd: analog supply voltage
+*.include vco_sub.cir
+*xvco buf d_digout cont dd ro_vco
+.include vco_sub_new.cir
+xvco buf d_digout cont dd d_osc_vco 
+
+.option noacct
+
+.control
+set xtrtol=2
+set dt = $curplot
+set curplot = new
+set curplottitle = "Frequency versus voltage"
+set freq_volt = $curplot $ store its name to 'freq_volt'
+setplot $freq_volt
+let vcovec=vector(5)
+let foscvec=vector(5)
+setplot $dt
+alter vco 0.5
+tran 0.1n $&simtime 0
+let {$freq_volt}.vcovec[0]=v(cont)
+linearize buf
+fft buf
+* start meas at freq > 0 to skip large dc part
+meas sp fosc MAX_AT buf from=1e3 to=1e9
+let {$freq_volt}.foscvec[0]=fosc
+plot d_digout xlimit 140n 160n
+reset
+alter vco 1
+tran 0.1n $&simtime 0
+let {$freq_volt}.vcovec[1]=v(cont)
+linearize buf
+fft buf
+meas sp fosc MAX_AT buf from=1e3 to=1e9
+let {$freq_volt}.foscvec[1]=fosc
+plot d_digout xlimit 140n 160n
+reset
+alter vco 1.5
+tran 0.1n $&simtime 0
+let {$freq_volt}.vcovec[2]=v(cont)
+linearize buf
+fft buf
+meas sp fosc MAX_AT buf from=1e3 to=1e9
+let {$freq_volt}.foscvec[2]=fosc
+plot d_digout xlimit 140n 160n
+reset
+alter vco 2
+tran 0.1n $&simtime 0
+let {$freq_volt}.vcovec[3]=v(cont)
+linearize buf
+fft buf
+meas sp fosc MAX_AT buf from=1e3 to=1e9
+let {$freq_volt}.foscvec[3]=fosc
+plot d_digout xlimit 140n 160n
+reset
+alter vco 2.5
+tran 0.1n $&simtime 0
+let {$freq_volt}.vcovec[4]=v(cont)
+linearize buf
+fft buf
+meas sp fosc MAX_AT buf from=1e3 to=1e9
+let {$freq_volt}.foscvec[4]=fosc
+plot d_digout xlimit 140n 160n
+plot tran1.buf tran3.buf tran5.buf tran7.buf tran9.buf xlimit 140n 160n
+plot mag(sp2.buf) mag(sp4.buf) mag(sp6.buf) mag(sp8.buf) mag(sp10.buf) xlimit 100e6 1100e6
+setplot $freq_volt
+settype frequency foscvec
+settype voltage vcovec
+plot foscvec vs vcovec
+print vcovec foscvec
+rusage
+.endc
+
+*model = bsim3v3
+*Berkeley Spice Compatibility 
+* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
+.model N1 NMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=9.36e-8 Wint=1.47e-7
++Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612 
++Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2 
++Nlx= 3.52291E-08  W0= 1.163e-6 
++K3b= 2.233 
++Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11 
++Rdsw= 650  U0= 388.3203 wr=1
++A0= .3496967 Ags=.1    B0=0.546    B1= 1   
++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
++Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9 
++Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04 
++Cdsc=-2.147181E-05   
++Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0 
++ Cdscd =  0 Prwg =  0 
++Eta0= 1.0281729E-02  Etab=-5.042203E-03 
++Dsub= .31871233 
++Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03 
++Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
++Pvag= 0 delta=0.01
++ Wl =  0 Ww = -1.420242E-09 Wwl =  0 
++ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10 
++ Lw =  0 Lwl =  0 Lln =  .316394 
++ Lwn =  0
++kt1=-.3  kt2=-.051 
++At= 22400 
++Ute=-1.48 
++Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10 
++Kt1l=0 Prt=764.3
+
+.model P1 PMOS
+*+version = 3.2.4
++version = 3.3.0
++Level=        8 
++Tnom=27.0
++Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
++Lint=6.23e-8 Wint=1.22e-7
++Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82 
++Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677 
++Nlx= 1.28e-8  W0= 2.1e-6 
++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 
++Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11 
++ Rdsw= 460  U0= 138.7609 
++A0= .4716551 Ags=0.12 
++Keta=-1.871516E-03  A1= .3417965  A2= 0.83 
++Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03 
++Cdsc= 8.937517E-04 
++Cdscb= 1.45e-4  Cdscd=1.04e-4
++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
++Eta0= 6.024776E-02  Etab=-4.64593E-03 
++Dsub= .23222404 
++Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3 
++Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09 
++Pvag= 0 
++kt1= -0.25  kt2= -0.032 prt=64.5 
++At= 33000 
++Ute= -1.5 
++Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0 
++Kt1l=0
+
+.end
diff --git a/Windows/spice/examples/xspice/pll/vco_sub.cir b/Windows/spice/examples/xspice/pll/vco_sub.cir
new file mode 100644
index 00000000..77f87360
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/vco_sub.cir
@@ -0,0 +1,67 @@
+* VCO: 7 stage Ring-Osc. made of gain cells BSIM3
+* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495
+* 150 MHz to 900 MHz with control voltage 2.5 to 0.5 V at 3.3 V supply
+* BSIM 3 model data for transistors in main file pll-xspice.cir
+
+***** ring oscillator as voltage controlled oscillator *************** 
+* name: ro_vco
+* aout analog out
+* dout digital out 
+* cont control voltage
+* dd supply voltage
+
+.subckt ro_vco aout dout cont dd
+* ignition circuit (not needed)
+* feedback between in and out, pulse to help start oscillation
+vin inm1 outp7 dc 0
+*vin inm1 outp7 dc 2.5 pulse 2.5 0 0.1n 5n 1 1 1
+
+*vin2 inp1 outp7 dc -0.5 pulse -0.5 0 0.1n 5n 1 1 1
+vin2 inp1 outm7 dc 0
+
+
+vss ss 0 dc 0
+ve  sub  0 dc 0
+vpe well 0 dc 3.3
+
+
+* gain cell
+.subckt gaincell dd ss sub well co in- in+ out- out+
+mn1  out- in+   ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
+mn2  out- out+  ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
+mn3  out+ out-  ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
+mn4  out+ in-   ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
+mp1  out- co    dd  well  p1  w=4u l=0.35u  AS=7p AD=7p PS=6u PD=6u
+mp2  out+ co    dd  well  p1  w=4u l=0.35u  AS=7p AD=7p PS=6u PD=6u
+.ends gaincell
+
+* inverter
+.subckt inv2 dd ss sub well in out
+mn1  out in  ss  sub  n1  w=6u  l=0.35u  AS=12p AD=12p PS=16u PD=16u
+mp1  out in  dd  well  p1  w=12u l=0.35u  AS=24p AD=24p PS=28u PD=28u
+.ends inv2
+
+* inverter
+.subckt inv1 dd ss sub well in out
+mn1  out in  ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
+mp1  out in  dd  well  p1  w=4u l=0.35u  AS=7p AD=7p PS=6u PD=6u
+.ends inv1
+
+* chain of 25 inverters + output buffer
+xinv1 dd ss sub well cont inm1  inp1  outm1 outp1 gaincell 
+xinv2 dd ss sub well cont outp1 outm1 outm2 outp2 gaincell 
+xinv3 dd ss sub well cont outp2 outm2 outm3 outp3 gaincell
+xinv4 dd ss sub well cont outp3 outm3 outm4 outp4 gaincell
+xinv5 dd ss sub well cont outp4 outm4 outm5 outp5 gaincell
+xinv6 dd ss sub well cont outp5 outm5 outm6 outp6 gaincell
+xinv7 dd ss sub well cont outp6 outm6 outm7 outp7 gaincell
+* analog out (two stage buffer)
+xinv11 dd 0 sub well outm1 outm2 inv1
+xinv12 dd 0 sub well outm2 aout inv2
+cout  aout 0 0.2pF
+*digital out
+abridge1 [aout] [dout] adc_buff
+.model adc_buff adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
+.ends ro_vco
+******************************************************************
+
diff --git a/Windows/spice/examples/xspice/pll/vco_sub_new.cir b/Windows/spice/examples/xspice/pll/vco_sub_new.cir
new file mode 100644
index 00000000..229ccf84
--- /dev/null
+++ b/Windows/spice/examples/xspice/pll/vco_sub_new.cir
@@ -0,0 +1,30 @@
+***** XSPICE digital controlled oscillator d_osc as vco *************** 
+* 150 MHz to 900 MHz
+* name: d_osc_vco
+* aout analog out
+* dout digital out 
+* cont control voltage
+* dd supply voltage
+
+.subckt d_osc_vco aout dout cont dd
+* curve fitting to ro_vco 'measured' data
+Bfit fitted 0 v = (-58256685.71*v(cont)*v(cont) - 186386142.9*v(cont) + 988722980)/10.
+
+*a5 fitted dout var_clock
+*.model var_clock d_osc(cntl_array = [1.0e7 5.0e7 9.0e7]
+*+ freq_array = [1.0e8 5.0e8 9.0e8]
+
+* linear interpolation, input data from measured ro vco
+a5 cont dout var_clock
+.model var_clock d_osc(cntl_array = [0.5 1 1.5 2 2.5]
++ freq_array = [8.790820e+008 7.472197e+008 5.799500e+008 3.772727e+008 1.611650e+008]
++ duty_cycle = 0.5 init_phase = 180.0
++ rise_delay = 1e-10 fall_delay=1e-10)
+
+*generate an analog output for plotting
+abridge-fit [dout] [aout] dac1
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-10
++ t_fall = 1e-10)
+
+.ends d_osc_vco
diff --git a/Windows/spice/examples/xspice/sine.m b/Windows/spice/examples/xspice/sine.m
new file mode 100644
index 00000000..c01fbe9a
--- /dev/null
+++ b/Windows/spice/examples/xspice/sine.m
@@ -0,0 +1,264 @@
+# Created by Octave 3.4.0, Mon Jun 06 10:16:19 2011 CEST <sailer@xbox360.hq.axsem.com>
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+ 9.804687499999999e-07 -0.122410675199216 0.99247953459871
+ 9.84375e-07 -0.09801714032956051 0.9951847266721969
+ 9.882812499999999e-07 -0.07356456359966741 0.9972904566786902
+ 9.921875e-07 -0.04906767432741809 0.9987954562051724
+ 9.960937499999999e-07 -0.02454122852291245 0.9996988186962042
+ 1e-06 -2.449293598294706e-16 1
+
+
diff --git a/Windows/spice/examples/xspice/xspice_c1.cir b/Windows/spice/examples/xspice/xspice_c1.cir
new file mode 100644
index 00000000..022d9138
--- /dev/null
+++ b/Windows/spice/examples/xspice/xspice_c1.cir
@@ -0,0 +1,22 @@
+A Berkeley SPICE3 compatible circuit
+*
+* This circuit contains only Berkeley SPICE3 components.
+*
+* The circuit is an AC coupled transistor amplifier with
+* a sinewave input at node "1", a gain of approximately -3.9,
+* and output on node "coll".
+*
+.tran 1e-5 2e-3
+*
+vcc vcc 0 12.0
+vin 1 0 0.0 ac 1.0 sin(0 1 1k)
+ccouple 1 base 10uF
+rbias1 vcc base 100k
+rbias2 base 0 24k
+q1 coll base emit generic
+rcollector vcc coll 3.9k
+remitter emit 0 1k
+*
+.model generic npn
+*
+.end
diff --git a/Windows/spice/examples/xspice/xspice_c2.cir b/Windows/spice/examples/xspice/xspice_c2.cir
new file mode 100644
index 00000000..5c66bdd1
--- /dev/null
+++ b/Windows/spice/examples/xspice/xspice_c2.cir
@@ -0,0 +1,16 @@
+A transistor amplifier circuit  
+*  
+.tran 1e-5 2e-3  
+*  
+vin 1 0 0.0 ac 1.0 sin(0 1 1k)  
+*  
+ccouple 1 in 10uF 
+rzin in 0 19.35k  
+*  
+aamp in aout gain_block  
+.model gain_block gain (gain = -3.9 out_offset = 7.003)  
+* 
+rzout aout coll 3.9k 
+rbig coll 0 1e12 
+*  
+.end
diff --git a/Windows/spice/examples/xspice/xspice_c3.cir b/Windows/spice/examples/xspice/xspice_c3.cir
new file mode 100644
index 00000000..4c536293
--- /dev/null
+++ b/Windows/spice/examples/xspice/xspice_c3.cir
@@ -0,0 +1,97 @@
+Mixed IO types  
+* This circuit contains a mixture of IO types, including  
+* analog, digital, user-defined (real), and 'null'. 
+*  
+* The circuit demonstrates the use of the digital and 
+* user-defined node capability to model system-level designs 
+* such as sampled-data filters. The simulated circuit 
+* contains a digital oscillator enabled after 100us. The 
+* square wave oscillator output is divided by 8 with a 
+* ripple counter. The result is passed through a digital 
+* filter to convert it to a sine wave. 
+* 
+.tran 1e-5 1e-3 
+.save all
+* 
+v1 1 0 0.0 pulse(0 1 1e-4 1e-6) 
+r1 1 0 1k 
+* 
+abridge1 [1] [enable] atod 
+.model atod adc_bridge 
+* 
+aclk [enable clk] clk nand 
+.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5) 
+* 
+adiv2 div2_out clk NULL NULL NULL div2_out dff 
+adiv4 div4_out div2_out NULL NULL NULL div4_out dff
+adiv8 div8_out div4_out NULL NULL NULL div8_out dff 
+.model dff d_dff 
+* 
+abridge2 div8_out enable filt_in node_bridge2 
+.model node_bridge2 d_to_real (zero=-1 one=1) 
+* 
+xfilter filt_in clk filt_out dig_filter 
+* 
+abridge3 filt_out a_out node_bridge3 
+.model node_bridge3 real_to_v 
+* 
+rlpf1 a_out oa_minus 10k 
+* 
+xlpf 0 oa_minus lpf_out opamp 
+* 
+rlpf2 oa_minus lpf_out 10k 
+clpf lpf_out oa_minus 0.01uF 
+* 
+* 
+.subckt dig_filter filt_in clk filt_out 
+* 
+.model n0 real_gain (gain=1.0) 
+.model n1 real_gain (gain=2.0) 
+.model n2 real_gain (gain=1.0) 
+.model g1 real_gain (gain=0.125) 
+.model zm1 real_delay 
+.model d0a real_gain (gain=-0.75) 
+.model d1a real_gain (gain=0.5625) 
+.model d0b real_gain (gain=-0.3438) 
+.model d1b real_gain (gain=1.0) 
+* 
+an0a filt_in x0a n0 
+an1a filt_in x1a n1 
+an2a filt_in x2a n2 
+* 
+az0a x0a clk x1a zm1 
+az1a x1a clk x2a zm1 
+* 
+ad0a x2a x0a d0a 
+ad1a x2a x1a d1a 
+* 
+az2a x2a filt1_out g1 
+az3a filt1_out clk filt2_in zm1 
+* 
+an0b filt2_in x0b n0 
+an1b filt2_in x1b n1 
+an2b filt2_in x2b n2 
+*
+az0b x0b clk x1b zm1 
+az1b x1b clk x2b zm1 
+* 
+ad0 x2b x0b d0b 
+ad1 x2b x1b d1b 
+* 
+az2b x2b clk filt_out zm1 
+* 
+.ends dig_filter 
+* 
+* 
+.subckt opamp plus minus out 
+* 
+r1 plus minus 300k 
+a1 %vd (plus minus) outint lim 
+.model lim limit (out_lower_limit = -12 out_upper_limit = 12 
++ fraction = true limit_range = 0.2 gain=300e3) 
+r3 outint out 50.0 
+r2 out 0 1e12 
+* 
+.ends opamp
+*  
+.end