Merge pull request #161 from rahulp13/installersi2.1

fixed key issue for ubuntu 20+; updated installers for windows os

10 files changed, 0 insertions, 814 deletions

diff --git a/Windows/spice/examples/xspice/pll/README b/Windows/spice/examples/xspice/pll/README
deleted file mode 100644
index f5c38b39..00000000
--- a/Windows/spice/examples/xspice/pll/README
+++ /dev/null
@@ -1,39 +0,0 @@
-This directory contains a mixed mode pll, combining
-ngspice and XSPICE circuit blocks.
-The pll consists of the following blocks:
-
-** voltage controlled oscillator:
-vco_sub.cir
-   7 stage ring oscillator with gain cells, CMOS devices
-or
-vco_sub_new.cir
-   vco made from code model d_osc, cntl_array/freq_array data
-   are gained by running test-vco.cir with vco_sub.cir
-
-** digital divider and frequency reference:
-pll-xspice.cir
-
-** phase frequency detector:
-f-p-det-d-sub.cir
-
-** loop filter:
-loop-filter.cir
-   switched current sources as charge pump, 2nd order
-   passive RC filter
-or
-loop-filter-2.cir
-   transistors as switches for charge pump, 2nd or 3rd
-   order passive RC filters
-
-** main simulation control:
-pll-xspice.cir
-
-Two test files are included:
-test-vco.cir simulates vco frequency versus control voltage
-test-f-p-det.cir simulates the phase frequency detector and the loop filter.
-
-The main building blocks are organised as subcircuits.
-
-main simulation control with three reference frequencies:
-pll-xspice-fstep.cir
-   simulates two steps of the reference in one simulation run
diff --git a/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir b/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir
deleted file mode 100644
index cdd5af9e..00000000
--- a/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* frequency-phase detector according to
-* http://www.uwe-kerwien.de/pll/pll-phasenvergleich.htm
-
-.subckt f-p-det d_R d_V d_U d_U_ d_D d_D_
-
-aa1 [d_U d_D] d_rset and1
-.model and1 d_and(rise_delay = 1e-10 fall_delay = 0.1e-9
-+ input_load = 0.5e-12)
-
-ad1 d_d1 d_R d_d0 d_rset d_U d_U_ flop1
-ad2 d_d1 d_V d_d0 d_rset d_D d_D_ flop1
-.model flop1 d_dff(clk_delay = 1.0e-10 set_delay = 1.0e-10
-+ reset_delay = 1.0e-10 ic = 2 rise_delay = 1.0e-10
-+ fall_delay = 1e-10)
-
-.ends f-p-det
diff --git a/Windows/spice/examples/xspice/pll/loop-filter-2.cir b/Windows/spice/examples/xspice/pll/loop-filter-2.cir
deleted file mode 100644
index 3d093167..00000000
--- a/Windows/spice/examples/xspice/pll/loop-filter-2.cir
+++ /dev/null
@@ -1,50 +0,0 @@
-* loop filter for pll
-* in: d_up d_down digital data
-* out: vout, vco control voltage
-* using transistors to switch current
-* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm
-* digital input d_Un d_D
-* anlog output vout
-
-
-.subckt loopf d_Un d_D vout
-
-.param initcond=2.5
-
-vdd dd 0 dc 'vcc'
-vss ss 0 dc 0
-
-* "driver" circuit, digital in, analog out
-abridge-f1 [d_Un d_D] [u1n d1] dac1
-.model dac1 dac_bridge(out_low = 0 out_high = 'vcc' out_undef = 'vcc/2'
-+ input_load = 5.0e-12 t_rise = 1e-10
-+ t_fall = 1e-10)
-
-* uses BSIM3 model parameters from pll-xspice_2.cir
-* transistors as switches
-mnd  dra d1  ss  ss  n1  w=12u  l=0.35u  AS=24p AD=24p PS=28u PD=28u
-mpd  dra u1n  dd  dd  p1  w=24u l=0.35u  AS=48p AD=48p PS=52u PD=52u
-
-*** passive filter elements ***
-*third order filter
-*parameters absolutely _not_ optimised
-*better check
-* http://www.national.com/assets/en/boards/deansbook4.pdf
-*to do so
-.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(int1)='initcond' v(u1n)='vcc' v(d1)=0
-R1 dra int1 300
-R2 int1 c1 200
-C1 c1 0 10n
-C2 int1 0 5n
-R3 int1 vout 50
-C3 vout 0 0.5n
-
-*second order filter
-*parameters not optimized
-*.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(u1n)='vcc' v(d1)=0
-*R1 dra vout 300
-*R2 vout c1 200
-*C1 c1 0 10n
-*C2 vout 0 5n
-
-.ends loopf
diff --git a/Windows/spice/examples/xspice/pll/loop-filter.cir b/Windows/spice/examples/xspice/pll/loop-filter.cir
deleted file mode 100644
index a83ebb7a..00000000
--- a/Windows/spice/examples/xspice/pll/loop-filter.cir
+++ /dev/null
@@ -1,31 +0,0 @@
-* loop filter for pll
-* in: d_up d_down digital data
-* out: vout, vco control voltage
-* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm
-
-.subckt loopfe d_U d_D vout
-
-.param loadcur=5m
-.param initcond=2.5
-
-v1 vtop 0 1
-v2 vbot 0 -1
-
-abridge-f1 [d_U d_D] [u1 d1] dac1
-.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
-+ input_load = 5.0e-12 t_rise = 1e-10
-+ t_fall = 1e-10)
-
-*top switched current source
-Gtop vtop vout cur='loadcur*v(u1)'
-*bottom switched current source
-Gbot vout vbot cur='loadcur*v(d1)'
-
-*passive filter elements
-.ic v(vout)='initcond' v(c1)='initcond'
-R2 vout c1 200
-C1 c1 0 5n
-C2 vout 0 5n
-Rshunt vout 0 10000k
-
-.ends
diff --git a/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir b/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir
deleted file mode 100644
index 4f86fe9d..00000000
--- a/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir
+++ /dev/null
@@ -1,165 +0,0 @@
-* pll circuit using xspice code models
-* three frequencies generate steps in control voltage v(cont)
-
-.param vcc=3.3
-.param divisor=40
-.param fref=10e6
-.param fref2=9e6
-.param fref3=11e6
-.csparam simtime=45u
-.csparam f2='fref2'
-.csparam f3='fref3'
-
-* digital zero and one
-.global d_d0 d_d1
-
-vdd dd 0 dc 'vcc'
-
-* 10 MHz reference frequency
-* PULSE(V1 V2 TD TR TF PW PER)
-vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n  '1/fref/2' '1/fref')
-abridgeref [ref] [d_ref] adc_vbuf
-.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5)
-
-*digital zero
-vzero z 0 dc 0
-abridgev3 [z] [d_d0] adc_vbuf
-.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
-*digital one
-ainv1 d_d0 d_d1 invd1
-.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
-
-* vco
-* buf: analog out
-* d_digout: digital out
-* cont: analog control voltage
-* dd: analog supply voltage
-*.include vco_sub.cir
-*xvco buf d_digout cont dd ro_vco
-.include vco_sub_new.cir
-xvco buf d_digout cont dd d_osc_vco 
-
-* digital divider
-adiv1 d_digout d_divout divider
-.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2'
-+ i_count = 4 rise_delay = 1e-10
-+ fall_delay = 1e-10)
-
-* frequency phase detector
-.include f-p-det-d-sub.cir
-Xfpdet d_divout d_ref d_U d_Un d_D d_Dn  f-p-det
-
-* loop filter
-*2nd or 3rd order, transistors as switches
-.include loop-filter-2.cir
-Xlf d_Un d_D cont loopf
-* 2nd order, Exxxx voltage controlled current sources as 'switches'
-* loop filter current sources as charge pump
-*.include loop-filter.cir
-*Xlf d_U d_D cont loopfe
-
-* d to a for plotting
-abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1 d1] dac1 ; change to d_u or d_Un
-.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
-+ input_load = 5.0e-12 t_rise = 1e-10
-+ t_fall = 1e-10)
-
-.control
-save cont s1 s2 u1 d1
-iplot cont
-* calculate breakpoint for switching frequency
-let t1_3 = simtime/3
-set ti1_3 ="$&t1_3"
-let t2_3 = simtime/3*2
-set ti2_3 ="$&t2_3"
-stop when time=$ti1_3
-stop when time=$ti2_3
-* calculate new periods for f2
-let per2=1/f2
-let pw2 = per2/2
-let per3=1/f3
-let pw3 = per3/2
-*simulate
-tran 0.1n $&simtime 0 0.5n uic
-*change frequency after stopping
-* first pair of [] without spaces, second pair with spaces
-alter @vref[pulse] = [ 0 3.3 10n 1n 1n  $&pw2 $&per2 ]
-resume
-*another change after second stop
-alter @vref[pulse] = [ 0 3.3 10n 1n 1n  $&pw3 $&per3 ]
-resume
-rusage
-plot cont s1 s2+1.2 u1+2.4 d1+3.6 xlimit 15u 16u
-*plot cont
-.endc
-
-*model = bsim3v3
-*Berkeley Spice Compatibility 
-* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
-.model N1 NMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8 
-+Tnom=27.0
-+Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=9.36e-8 Wint=1.47e-7
-+Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612 
-+Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2 
-+Nlx= 3.52291E-08  W0= 1.163e-6 
-+K3b= 2.233 
-+Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11 
-+Rdsw= 650  U0= 388.3203 wr=1
-+A0= .3496967 Ags=.1    B0=0.546    B1= 1   
-+ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
-+Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9 
-+Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04 
-+Cdsc=-2.147181E-05   
-+Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0 
-+ Cdscd =  0 Prwg =  0 
-+Eta0= 1.0281729E-02  Etab=-5.042203E-03 
-+Dsub= .31871233 
-+Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03 
-+Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
-+Pvag= 0 delta=0.01
-+ Wl =  0 Ww = -1.420242E-09 Wwl =  0 
-+ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10 
-+ Lw =  0 Lwl =  0 Lln =  .316394 
-+ Lwn =  0
-+kt1=-.3  kt2=-.051 
-+At= 22400 
-+Ute=-1.48 
-+Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10 
-+Kt1l=0 Prt=764.3
-
-.model P1 PMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8 
-+Tnom=27.0
-+Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=6.23e-8 Wint=1.22e-7
-+Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82 
-+Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677 
-+Nlx= 1.28e-8  W0= 2.1e-6 
-+K3b= -0.24 Prwg=-0.001 Prwb=-0.323 
-+Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11 
-+ Rdsw= 460  U0= 138.7609 
-+A0= .4716551 Ags=0.12 
-+Keta=-1.871516E-03  A1= .3417965  A2= 0.83 
-+Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03 
-+Cdsc= 8.937517E-04 
-+Cdscb= 1.45e-4  Cdscd=1.04e-4
-+ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
-+Eta0= 6.024776E-02  Etab=-4.64593E-03 
-+Dsub= .23222404 
-+Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3 
-+Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09 
-+Pvag= 0 
-+kt1= -0.25  kt2= -0.032 prt=64.5 
-+At= 33000 
-+Ute= -1.5 
-+Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0 
-+Kt1l=0
-
-
-.end
diff --git a/Windows/spice/examples/xspice/pll/pll-xspice.cir b/Windows/spice/examples/xspice/pll/pll-xspice.cir
deleted file mode 100644
index 1d14368d..00000000
--- a/Windows/spice/examples/xspice/pll/pll-xspice.cir
+++ /dev/null
@@ -1,144 +0,0 @@
-* pll circuit using xspice code models
-* output frequency 400 MHz
-* locked to a 1 or 10 MHz reference
-
-.param vcc=3.3
-.param divisor=40
-.param fref=10e6
-.csparam simtime=25u
-
-.global d_d0 d_d1
-
-vdd dd 0 dc 'vcc'
-*vco cont 0 dc 1.9
-
-*PULSE(V1 V2 TD TR TF PW PER)
-* reference frequency selected by param fref
-* PULSE(V1 V2 TD TR TF PW PER)
-vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n  '1/fref/2' '1/fref')
-abridgeref [ref] [d_ref] adc_vbuf
-.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5)
-
-*digital zero
-vzero z 0 dc 0
-abridgev3 [z] [d_d0] adc_vbuf
-.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
-*digital one
-ainv1 d_d0 d_d1 invd1
-.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
-
-* vco
-* buf: analog out
-* d_digout: digital out
-* cont: analog control voltage
-* dd: analog supply voltage
-*.include vco_sub.cir
-*xvco buf d_digout cont dd ro_vco
-.include vco_sub_new.cir
-xvco buf d_digout cont dd d_osc_vco 
-
-* digital divider
-adiv1 d_digout d_divout divider
-.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2'
-+ i_count = 4 rise_delay = 1e-10
-+ fall_delay = 1e-10)
-
-* frequency phase detector
-.include f-p-det-d-sub.cir
-Xfpdet d_divout d_ref d_U d_Un d_D d_Dn  f-p-det
-
-* loop filters
-*2nd or 3rd order, transistors as switches
-.include loop-filter-2.cir
-Xlf d_Un d_D cont loopf
-* 2nd order, Exxxx voltage controlled current sources as 'switches'
-* loop filter current sources as charge pump
-*.include loop-filter.cir
-*Xlf d_U d_D cont loopfe
-
-* d to a for plotting
-abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un
-.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
-+ input_load = 5.0e-12 t_rise = 1e-10
-+ t_fall = 1e-10)
-
-.control
-save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory
-iplot cont
-tran 0.1n $&simtime uic
-rusage
-plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u
-plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m
-*plot cont
-.endc
-
-*model = bsim3v3
-*Berkeley Spice Compatibility 
-* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
-.model N1 NMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8 
-+Tnom=27.0
-+Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=9.36e-8 Wint=1.47e-7
-+Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612 
-+Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2 
-+Nlx= 3.52291E-08  W0= 1.163e-6 
-+K3b= 2.233 
-+Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11 
-+Rdsw= 650  U0= 388.3203 wr=1
-+A0= .3496967 Ags=.1    B0=0.546    B1= 1   
-+ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
-+Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9 
-+Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04 
-+Cdsc=-2.147181E-05   
-+Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0 
-+ Cdscd =  0 Prwg =  0 
-+Eta0= 1.0281729E-02  Etab=-5.042203E-03 
-+Dsub= .31871233 
-+Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03 
-+Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
-+Pvag= 0 delta=0.01
-+ Wl =  0 Ww = -1.420242E-09 Wwl =  0 
-+ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10 
-+ Lw =  0 Lwl =  0 Lln =  .316394 
-+ Lwn =  0
-+kt1=-.3  kt2=-.051 
-+At= 22400 
-+Ute=-1.48 
-+Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10 
-+Kt1l=0 Prt=764.3
-
-.model P1 PMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8 
-+Tnom=27.0
-+Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=6.23e-8 Wint=1.22e-7
-+Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82 
-+Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677 
-+Nlx= 1.28e-8  W0= 2.1e-6 
-+K3b= -0.24 Prwg=-0.001 Prwb=-0.323 
-+Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11 
-+ Rdsw= 460  U0= 138.7609 
-+A0= .4716551 Ags=0.12 
-+Keta=-1.871516E-03  A1= .3417965  A2= 0.83 
-+Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03 
-+Cdsc= 8.937517E-04 
-+Cdscb= 1.45e-4  Cdscd=1.04e-4
-+ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
-+Eta0= 6.024776E-02  Etab=-4.64593E-03 
-+Dsub= .23222404 
-+Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3 
-+Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09 
-+Pvag= 0 
-+kt1= -0.25  kt2= -0.032 prt=64.5 
-+At= 33000 
-+Ute= -1.5 
-+Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0 
-+Kt1l=0
-
-
-.end
diff --git a/Windows/spice/examples/xspice/pll/test-f-p-det.cir b/Windows/spice/examples/xspice/pll/test-f-p-det.cir
deleted file mode 100644
index 16060b9b..00000000
--- a/Windows/spice/examples/xspice/pll/test-f-p-det.cir
+++ /dev/null
@@ -1,114 +0,0 @@
-* test frequency-phase detector similar to 12040
-
-.param vcc=3.3
-.global d_d0 d_d1
-
-*PULSE(V1 V2 TD TR TF PW PER)
-v1 1 0 dc 0 pulse(0 'vcc' 10n 1n 1n 10n 20n)
-v2 2 0 dc 0 pulse(0 'vcc' 8n 1n 1n 10n 20n)
-
-*digital zero
-v3 3 0 dc 0
-abridgev1 [1 2 3] [d_sig1 d_sig2 d_d0] adc_vbuf
-.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
-*digital one
-ainv1 d_d0 d_d1 invd1
-.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10)
-
-Xfpdet d_sig1 d_sig2 d_U d_Un d_D d_Dn  f-p-det
-
-*.include f-p-det-sub.cir
-.include f-p-det-d-sub.cir
-
-* d to a for plotting
-abridge-w1 [d_sig1 d_sig2 d_U d_D] [s1 s2 u1 d1] dac1
-.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
-+ input_load = 5.0e-12 t_rise = 1e-10
-+ t_fall = 1e-10)
-
-* loop filters
-*2nd or 3rd order, transistors as switches
-.include loop-filter-2.cir
-Xlf d_Un d_D cont loopf
-* 2nd order, Exxxx voltage controlled current sources as 'switches'
-* loop filter current sources as charge pump
-*.include loop-filter.cir
-*Xlf d_U d_D cont loopfe
-
-.control
-set xtrtol=2
-tran 0.1n 1000n
-plot s1 s2+1.2 u1+2.4 d1+3.6 xlimit 140n 200n
-.endc
-
-
-*model = bsim3v3
-*Berkeley Spice Compatibility
-* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
-.model N1 NMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8
-+Tnom=27.0
-+Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=9.36e-8 Wint=1.47e-7
-+Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612
-+Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2
-+Nlx= 3.52291E-08  W0= 1.163e-6
-+K3b= 2.233
-+Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11
-+Rdsw= 650  U0= 388.3203 wr=1
-+A0= .3496967 Ags=.1    B0=0.546    B1= 1
-+ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
-+Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9
-+Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04
-+Cdsc=-2.147181E-05
-+Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0
-+ Cdscd =  0 Prwg =  0
-+Eta0= 1.0281729E-02  Etab=-5.042203E-03
-+Dsub= .31871233
-+Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03
-+Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
-+Pvag= 0 delta=0.01
-+ Wl =  0 Ww = -1.420242E-09 Wwl =  0
-+ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10
-+ Lw =  0 Lwl =  0 Lln =  .316394
-+ Lwn =  0
-+kt1=-.3  kt2=-.051
-+At= 22400
-+Ute=-1.48
-+Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10
-+Kt1l=0 Prt=764.3
-
-.model P1 PMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8
-+Tnom=27.0
-+Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=6.23e-8 Wint=1.22e-7
-+Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82
-+Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677
-+Nlx= 1.28e-8  W0= 2.1e-6
-+K3b= -0.24 Prwg=-0.001 Prwb=-0.323
-+Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11
-+ Rdsw= 460  U0= 138.7609
-+A0= .4716551 Ags=0.12
-+Keta=-1.871516E-03  A1= .3417965  A2= 0.83
-+Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03
-+Cdsc= 8.937517E-04
-+Cdscb= 1.45e-4  Cdscd=1.04e-4
-+ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
-+Eta0= 6.024776E-02  Etab=-4.64593E-03
-+Dsub= .23222404
-+Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3
-+Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09
-+Pvag= 0
-+kt1= -0.25  kt2= -0.032 prt=64.5
-+At= 33000
-+Ute= -1.5
-+Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0
-+Kt1l=0
-
-
-.end
diff --git a/Windows/spice/examples/xspice/pll/test_vco.cir b/Windows/spice/examples/xspice/pll/test_vco.cir
deleted file mode 100644
index 522eac00..00000000
--- a/Windows/spice/examples/xspice/pll/test_vco.cir
+++ /dev/null
@@ -1,158 +0,0 @@
-* Test of VCO: frequency versus control voltage
-* 7 stage Ring-Osc. made of gain cells BSIM3
-* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495
-* alternatively use d_osc code model
-* measure frequency of R.O. by fft 
-
-.param vcc=3.3
-.csparam simtime=500n
-
-vdd dd 0 dc 'vcc'
-vco cont 0 dc 2.5
-
-* vco
-* buf: analog out
-* d_digout: digital out
-* cont: analog control voltage
-* dd: analog supply voltage
-*.include vco_sub.cir
-*xvco buf d_digout cont dd ro_vco
-.include vco_sub_new.cir
-xvco buf d_digout cont dd d_osc_vco 
-
-.option noacct
-
-.control
-set xtrtol=2
-set dt = $curplot
-set curplot = new
-set curplottitle = "Frequency versus voltage"
-set freq_volt = $curplot $ store its name to 'freq_volt'
-setplot $freq_volt
-let vcovec=vector(5)
-let foscvec=vector(5)
-setplot $dt
-alter vco 0.5
-tran 0.1n $&simtime 0
-let {$freq_volt}.vcovec[0]=v(cont)
-linearize buf
-fft buf
-* start meas at freq > 0 to skip large dc part
-meas sp fosc MAX_AT buf from=1e3 to=1e9
-let {$freq_volt}.foscvec[0]=fosc
-plot d_digout xlimit 140n 160n
-reset
-alter vco 1
-tran 0.1n $&simtime 0
-let {$freq_volt}.vcovec[1]=v(cont)
-linearize buf
-fft buf
-meas sp fosc MAX_AT buf from=1e3 to=1e9
-let {$freq_volt}.foscvec[1]=fosc
-plot d_digout xlimit 140n 160n
-reset
-alter vco 1.5
-tran 0.1n $&simtime 0
-let {$freq_volt}.vcovec[2]=v(cont)
-linearize buf
-fft buf
-meas sp fosc MAX_AT buf from=1e3 to=1e9
-let {$freq_volt}.foscvec[2]=fosc
-plot d_digout xlimit 140n 160n
-reset
-alter vco 2
-tran 0.1n $&simtime 0
-let {$freq_volt}.vcovec[3]=v(cont)
-linearize buf
-fft buf
-meas sp fosc MAX_AT buf from=1e3 to=1e9
-let {$freq_volt}.foscvec[3]=fosc
-plot d_digout xlimit 140n 160n
-reset
-alter vco 2.5
-tran 0.1n $&simtime 0
-let {$freq_volt}.vcovec[4]=v(cont)
-linearize buf
-fft buf
-meas sp fosc MAX_AT buf from=1e3 to=1e9
-let {$freq_volt}.foscvec[4]=fosc
-plot d_digout xlimit 140n 160n
-plot tran1.buf tran3.buf tran5.buf tran7.buf tran9.buf xlimit 140n 160n
-plot mag(sp2.buf) mag(sp4.buf) mag(sp6.buf) mag(sp8.buf) mag(sp10.buf) xlimit 100e6 1100e6
-setplot $freq_volt
-settype frequency foscvec
-settype voltage vcovec
-plot foscvec vs vcovec
-print vcovec foscvec
-rusage
-.endc
-
-*model = bsim3v3
-*Berkeley Spice Compatibility 
-* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
-.model N1 NMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8 
-+Tnom=27.0
-+Nch= 2.498E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=9.36e-8 Wint=1.47e-7
-+Vth0= .6322    K1= .756  K2= -3.83e-2  K3= -2.612 
-+Dvt0= 2.812  Dvt1= 0.462  Dvt2=-9.17e-2 
-+Nlx= 3.52291E-08  W0= 1.163e-6 
-+K3b= 2.233 
-+Vsat= 86301.58  Ua= 6.47e-9  Ub= 4.23e-18  Uc=-4.706281E-11 
-+Rdsw= 650  U0= 388.3203 wr=1
-+A0= .3496967 Ags=.1    B0=0.546    B1= 1   
-+ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
-+Keta=-3.605872E-02  A1= 2.778747E-02  A2= .9 
-+Voff=-6.735529E-02  NFactor= 1.139926  Cit= 1.622527E-04 
-+Cdsc=-2.147181E-05   
-+Cdscb= 0  Dvt0w =  0 Dvt1w =  0 Dvt2w =  0 
-+ Cdscd =  0 Prwg =  0 
-+Eta0= 1.0281729E-02  Etab=-5.042203E-03 
-+Dsub= .31871233 
-+Pclm= 1.114846  Pdiblc1= 2.45357E-03  Pdiblc2= 6.406289E-03 
-+Drout= .31871233  Pscbe1= 5000000  Pscbe2= 5E-09 Pdiblcb = -.234
-+Pvag= 0 delta=0.01
-+ Wl =  0 Ww = -1.420242E-09 Wwl =  0 
-+ Wln =  0 Wwn =  .2613948 Ll =  1.300902E-10 
-+ Lw =  0 Lwl =  0 Lln =  .316394 
-+ Lwn =  0
-+kt1=-.3  kt2=-.051 
-+At= 22400 
-+Ute=-1.48 
-+Ua1= 3.31E-10  Ub1= 2.61E-19 Uc1= -3.42e-10 
-+Kt1l=0 Prt=764.3
-
-.model P1 PMOS
-*+version = 3.2.4
-+version = 3.3.0
-+Level=        8 
-+Tnom=27.0
-+Nch= 3.533024E+17  Tox=9E-09 Xj=1.00000E-07
-+Lint=6.23e-8 Wint=1.22e-7
-+Vth0=-.6732829 K1= .8362093  K2=-8.606622E-02  K3= 1.82 
-+Dvt0= 1.903801  Dvt1= .5333922  Dvt2=-.1862677 
-+Nlx= 1.28e-8  W0= 2.1e-6 
-+K3b= -0.24 Prwg=-0.001 Prwb=-0.323 
-+Vsat= 103503.2  Ua= 1.39995E-09  Ub= 1.e-19  Uc=-2.73e-11 
-+ Rdsw= 460  U0= 138.7609 
-+A0= .4716551 Ags=0.12 
-+Keta=-1.871516E-03  A1= .3417965  A2= 0.83 
-+Voff=-.074182  NFactor= 1.54389  Cit=-1.015667E-03 
-+Cdsc= 8.937517E-04 
-+Cdscb= 1.45e-4  Cdscd=1.04e-4
-+ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
-+Eta0= 6.024776E-02  Etab=-4.64593E-03 
-+Dsub= .23222404 
-+Pclm= .989  Pdiblc1= 2.07418E-02  Pdiblc2= 1.33813E-3 
-+Drout= .3222404  Pscbe1= 118000  Pscbe2= 1E-09 
-+Pvag= 0 
-+kt1= -0.25  kt2= -0.032 prt=64.5 
-+At= 33000 
-+Ute= -1.5 
-+Ua1= 4.312e-9 Ub1= 6.65e-19  Uc1= 0 
-+Kt1l=0
-
-.end
diff --git a/Windows/spice/examples/xspice/pll/vco_sub.cir b/Windows/spice/examples/xspice/pll/vco_sub.cir
deleted file mode 100644
index 77f87360..00000000
--- a/Windows/spice/examples/xspice/pll/vco_sub.cir
+++ /dev/null
@@ -1,67 +0,0 @@
-* VCO: 7 stage Ring-Osc. made of gain cells BSIM3
-* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495
-* 150 MHz to 900 MHz with control voltage 2.5 to 0.5 V at 3.3 V supply
-* BSIM 3 model data for transistors in main file pll-xspice.cir
-
-***** ring oscillator as voltage controlled oscillator *************** 
-* name: ro_vco
-* aout analog out
-* dout digital out 
-* cont control voltage
-* dd supply voltage
-
-.subckt ro_vco aout dout cont dd
-* ignition circuit (not needed)
-* feedback between in and out, pulse to help start oscillation
-vin inm1 outp7 dc 0
-*vin inm1 outp7 dc 2.5 pulse 2.5 0 0.1n 5n 1 1 1
-
-*vin2 inp1 outp7 dc -0.5 pulse -0.5 0 0.1n 5n 1 1 1
-vin2 inp1 outm7 dc 0
-
-
-vss ss 0 dc 0
-ve  sub  0 dc 0
-vpe well 0 dc 3.3
-
-
-* gain cell
-.subckt gaincell dd ss sub well co in- in+ out- out+
-mn1  out- in+   ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
-mn2  out- out+  ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
-mn3  out+ out-  ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
-mn4  out+ in-   ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
-mp1  out- co    dd  well  p1  w=4u l=0.35u  AS=7p AD=7p PS=6u PD=6u
-mp2  out+ co    dd  well  p1  w=4u l=0.35u  AS=7p AD=7p PS=6u PD=6u
-.ends gaincell
-
-* inverter
-.subckt inv2 dd ss sub well in out
-mn1  out in  ss  sub  n1  w=6u  l=0.35u  AS=12p AD=12p PS=16u PD=16u
-mp1  out in  dd  well  p1  w=12u l=0.35u  AS=24p AD=24p PS=28u PD=28u
-.ends inv2
-
-* inverter
-.subckt inv1 dd ss sub well in out
-mn1  out in  ss  sub  n1  w=2u  l=0.35u  AS=3p AD=3p PS=4u PD=4u
-mp1  out in  dd  well  p1  w=4u l=0.35u  AS=7p AD=7p PS=6u PD=6u
-.ends inv1
-
-* chain of 25 inverters + output buffer
-xinv1 dd ss sub well cont inm1  inp1  outm1 outp1 gaincell 
-xinv2 dd ss sub well cont outp1 outm1 outm2 outp2 gaincell 
-xinv3 dd ss sub well cont outp2 outm2 outm3 outp3 gaincell
-xinv4 dd ss sub well cont outp3 outm3 outm4 outp4 gaincell
-xinv5 dd ss sub well cont outp4 outm4 outm5 outp5 gaincell
-xinv6 dd ss sub well cont outp5 outm5 outm6 outp6 gaincell
-xinv7 dd ss sub well cont outp6 outm6 outm7 outp7 gaincell
-* analog out (two stage buffer)
-xinv11 dd 0 sub well outm1 outm2 inv1
-xinv12 dd 0 sub well outm2 aout inv2
-cout  aout 0 0.2pF
-*digital out
-abridge1 [aout] [dout] adc_buff
-.model adc_buff adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5')
-.ends ro_vco
-******************************************************************
-
diff --git a/Windows/spice/examples/xspice/pll/vco_sub_new.cir b/Windows/spice/examples/xspice/pll/vco_sub_new.cir
deleted file mode 100644
index 229ccf84..00000000
--- a/Windows/spice/examples/xspice/pll/vco_sub_new.cir
+++ /dev/null
@@ -1,30 +0,0 @@
-***** XSPICE digital controlled oscillator d_osc as vco *************** 
-* 150 MHz to 900 MHz
-* name: d_osc_vco
-* aout analog out
-* dout digital out 
-* cont control voltage
-* dd supply voltage
-
-.subckt d_osc_vco aout dout cont dd
-* curve fitting to ro_vco 'measured' data
-Bfit fitted 0 v = (-58256685.71*v(cont)*v(cont) - 186386142.9*v(cont) + 988722980)/10.
-
-*a5 fitted dout var_clock
-*.model var_clock d_osc(cntl_array = [1.0e7 5.0e7 9.0e7]
-*+ freq_array = [1.0e8 5.0e8 9.0e8]
-
-* linear interpolation, input data from measured ro vco
-a5 cont dout var_clock
-.model var_clock d_osc(cntl_array = [0.5 1 1.5 2 2.5]
-+ freq_array = [8.790820e+008 7.472197e+008 5.799500e+008 3.772727e+008 1.611650e+008]
-+ duty_cycle = 0.5 init_phase = 180.0
-+ rise_delay = 1e-10 fall_delay=1e-10)
-
-*generate an analog output for plotting
-abridge-fit [dout] [aout] dac1
-.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
-+ input_load = 5.0e-12 t_rise = 1e-10
-+ t_fall = 1e-10)
-
-.ends d_osc_vco