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| author | rahulp13 | 2021-01-07 18:22:29 +0530 |
|---|---|---|
| committer | rahulp13 | 2021-01-07 18:22:29 +0530 |
| commit | d4fd47ecf77597595d3f4fa72fd5334a5fe7417b (patch) | |
| tree | 28095229ec3035d15c569fbedac83cf5876aa196 /Windows/spice/examples/xspice/original-examples | |
| parent | 376e748df438933088721286402462dffd6367c0 (diff) | |
| parent | 63e3156454f39732a3101c29d42b473a89ca68d2 (diff) | |
| download | eSim-d4fd47ecf77597595d3f4fa72fd5334a5fe7417b.tar.gz eSim-d4fd47ecf77597595d3f4fa72fd5334a5fe7417b.tar.bz2 eSim-d4fd47ecf77597595d3f4fa72fd5334a5fe7417b.zip | |
Merge windows installer updates with linux installer
Diffstat (limited to 'Windows/spice/examples/xspice/original-examples')
54 files changed, 0 insertions, 2412 deletions
diff --git a/Windows/spice/examples/xspice/original-examples/analog_models1_ac.deck b/Windows/spice/examples/xspice/original-examples/analog_models1_ac.deck deleted file mode 100644 index 6467c2bd..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models1_ac.deck +++ /dev/null @@ -1,67 +0,0 @@ -Code Model Test - AC: gain, summer, mult, divide, pwl -* -* -*** analysis type *** -.ac dec 10 10 1000 -* -*** input sources *** -* -v1 1 0 1.0 AC 1.0 0.0 -* -v2 2 0 1.0 AC 1.0 0.0 -* -v3 3 0 DC 2.0 -* -v4 4 0 0.5 AC 0.5 0.0 -* -*** gain block *** -a1 1 10 gain1 -.model gain1 gain (in_offset=0.0 gain=2.0 out_offset=0.0) -* -* -*** summer block *** -a2 [1 2] 20 summer1 -.model summer1 summer (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=1.0 out_offset=0.0) -* -* -*** mult block *** -a3 [1 3] 30 mult1 -.model mult1 mult (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=1.0 out_offset=0.0) -* -* -*** divider block *** -a4 1 3 40 divide1 -.model divide1 divide (num_offset=0.0 num_gain=1.0 den_offset=0.0 den_gain=1.0 -+ den_lower_limit=1.0e-10 den_domain=1.0e-16 -+ fraction=false out_gain=1.0 out_offset=0.0) -* -* -*** pwl block *** -a5 4 50 pwl1 -.model pwl1 pwl (x_array=[-1.0 0.0 1.0 2.0 3.0 4.0 5.0] -+ y_array=[-1.0 0.0 1.0 4.0 4.5 5.0 5.0] -+ input_domain=0.01 fraction=TRUE) -* -* -*** resistors to ground *** -r1 1 0 1k -r2 2 0 1k -r3 3 0 1k -r4 4 0 1k -* -r10 10 0 1k -r20 20 0 1k -r30 30 0 1k -r40 40 0 1k -r50 50 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models1_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models1_dc.deck deleted file mode 100644 index 4ad6f0c8..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models1_dc.deck +++ /dev/null @@ -1,61 +0,0 @@ -Code Model Test - DC: gain, summer, mult, divide, pwl -* -* -*** analysis type *** -.op -* -*** input sources *** -v1 1 0 DC 2 -* -v2 2 0 DC 2 -* -*** gain block *** -a1 1 10 gain1 -.model gain1 gain (in_offset=0.0 gain=2.0 out_offset=0.0) -* -* -*** summer block *** -a2 [1 2] 20 summer1 -.model summer1 summer (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=1.0 out_offset=0.0) -* -* -*** mult block *** -a3 [1 1] 30 mult1 -.model mult1 mult (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=0.1 out_offset=0.0) -* -* -*** divider block *** -a4 2 1 40 divide1 -.model divide1 divide (num_offset=0.0 num_gain=1.0 den_offset=0.0 den_gain=1.0 -+ den_lower_limit=1.0e-10 den_domain=1.0e-16 -+ fraction=false out_gain=1.0 out_offset=0.0) -* -* -*** pwl block *** -a5 1 50 pwl1 -.model pwl1 pwl (x_array=[-1.0 0.0 1.0 2.0 3.0 4.0 5.0] -+ y_array=[ 0.0 0.0 1.0 4.0 4.5 5.0 5.0] -+ input_domain=0.01 fraction=TRUE) -* -* -*** resistors to ground *** -r1 1 0 1k -r2 2 0 1k -r3 3 0 1k -* -r10 10 0 1k -r20 20 0 1k -r30 30 0 1k -r40 40 0 1k -r50 50 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models1_swept_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models1_swept_dc.deck deleted file mode 100644 index e211325b..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models1_swept_dc.deck +++ /dev/null @@ -1,61 +0,0 @@ -Code Model Test - Swept DC: gain, summer, mult, divide, pwl -* -* -*** analysis type *** -.dc v1 .1 10 .1 -* -*** input sources *** -v1 1 0 DC 2 -* -v2 2 0 DC 2 -* -*** gain block *** -a1 1 10 gain1 -.model gain1 gain (in_offset=0.0 gain=2.0 out_offset=0.0) -* -* -*** summer block *** -a2 [1 2] 20 summer1 -.model summer1 summer (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=1.0 out_offset=0.0) -* -* -*** mult block *** -a3 [1 1] 30 mult1 -.model mult1 mult (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=0.1 out_offset=0.0) -* -* -*** divider block *** -a4 2 1 40 divide1 -.model divide1 divide (num_offset=0.0 num_gain=1.0 den_offset=0.0 den_gain=1.0 -+ den_lower_limit=1.0e-10 den_domain=1.0e-16 -+ fraction=false out_gain=1.0 out_offset=0.0) -* -* -*** pwl block *** -a5 1 50 pwl1 -.model pwl1 pwl (x_array=[-1.0 0.0 1.0 2.0 3.0 4.0 5.0] -+ y_array=[ 0.0 0.0 1.0 4.0 4.5 5.0 5.0] -+ input_domain=0.01 fraction=TRUE) -* -* -*** resistors to ground *** -r1 1 0 1k -r2 2 0 1k -r3 3 0 1k -* -r10 10 0 1k -r20 20 0 1k -r30 30 0 1k -r40 40 0 1k -r50 50 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models1_transient.deck b/Windows/spice/examples/xspice/original-examples/analog_models1_transient.deck deleted file mode 100644 index a4967d27..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models1_transient.deck +++ /dev/null @@ -1,62 +0,0 @@ -Code Model Test - Transient: gain, summer, mult, divide, pwl -* -* -*** analysis type *** -.tran .1s 10s -* -*** input sources *** -* -v1 1 0 DC PWL(0 0 10 10) -* -v2 2 0 DC 2 -* -*** gain block *** -a1 1 10 gain1 -.model gain1 gain (in_offset=0.0 gain=2.0 out_offset=0.0) -* -* -*** summer block *** -a2 [1 2] 20 summer1 -.model summer1 summer (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=1.0 out_offset=0.0) -* -* -*** mult block *** -a3 [1 1] 30 mult1 -.model mult1 mult (in_offset=[0.0 0.0] in_gain=[1.0 1.0] -+ out_gain=0.1 out_offset=0.0) -* -* -*** divider block *** -a4 2 1 40 divide1 -.model divide1 divide (num_offset=0.0 num_gain=1.0 den_offset=0.0 den_gain=1.0 -+ den_lower_limit=0.1 den_domain=1.0e-16 -+ fraction=false out_gain=1.0 out_offset=0.0) -* -* -*** pwl block *** -a5 1 50 pwl1 -.model pwl1 pwl (x_array=[-1.0 0.0 1.0 2.0 3.0 4.0 5.0] -+ y_array=[ 0.0 0.0 1.0 4.0 4.5 5.0 5.0] -+ input_domain=0.01 fraction=TRUE) -* -* -*** resistors to ground *** -r1 1 0 1k -r2 2 0 1k -r3 3 0 1k -* -r10 10 0 1k -r20 20 0 1k -r30 30 0 1k -r40 40 0 1k -r50 50 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models2_ac.deck b/Windows/spice/examples/xspice/original-examples/analog_models2_ac.deck deleted file mode 100644 index 0b450c80..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models2_ac.deck +++ /dev/null @@ -1,66 +0,0 @@ -Code Model Test - Swept DC: int, d_dt, s_xfer, core, lcouple -* -* -*** analysis type *** -.ac dec 10 10 1000 -* -* -*** input sources *** -* -v1 1 0 1.0 AC 1.0 0.0 -* -* -*** integrator block *** -a1 1 10 int1 -.model int1 int (in_offset=0.0 gain=2.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 out_ic=0.0) -* -* -*** differentiator block *** -a2 1 20 d_dt1 -.model d_dt1 d_dt (out_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6) -* -* -*** s_xfer block *** -a3 1 30 filter1 -.model filter1 s_xfer (in_offset=0.0 gain=1.0 num_coeff=[1.0] -+ den_coeff=[1.0 1.414214 1.0] int_ic=[0.0 0.0] -+ denormalized_freq=628.0) -* -* -* -*** magnetic core & inductive coupling *** -v40 45 46 0.0 -a4 40 45 core1 -.model core1 core (H_array=[-2.0 -1.0 1.0 2.0] -+ B_array=[-2.0 -1.0 1.0 2.0] -+ area=1.0 length=1.0 input_domain=1.0e-6 -+ fraction=TRUE mode=1 -+ in_low=-1.0 in_high=1.0 hyst=0.5 -+ out_lower_limit=-1.0 out_upper_limit=1.0) -* -* -r5 1 50 100.0 -a5 (50 0) (40 46) inductor1 -.model inductor1 lcouple (num_turns=10) -* -* -*** resistors to ground *** -r1 1 0 1k -* -r10 10 0 1e12 -r20 20 0 1e12 -r30 30 0 1e12 -r40 40 0 1e12 -r45 45 0 1e12 -r50 50 0 1e12 -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models2_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models2_dc.deck deleted file mode 100644 index 66a612e4..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models2_dc.deck +++ /dev/null @@ -1,63 +0,0 @@ -Code Model Test - DC: int, d_dt, s_xfer, core, lcouple -* -* -*** analysis type *** -.op -* -*** input sources *** -v1 1 0 DC 1.0 -* -* -* -* -*** integrator block *** -a1 1 10 int1 -.model int1 int (in_offset=0.0 gain=2.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 out_ic=0.0) -* -* -*** differentiator block *** -a2 1 20 d_dt1 -.model d_dt1 d_dt (out_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6) -* -* -*** s_xfer block *** -a3 1 30 filter1 -.model filter1 s_xfer (in_offset=0.0 gain=1.0 num_coeff=[1.0] -+ den_coeff=[1.0 1.425625 1.516203] int_ic=[0.0 0.0] -+ denormalized_freq=6283.2) -* -* -*** magnetic core & inductive coupling *** -a4 40 45 core1 -.model core1 core (H_array=[-2.0 -1.0 1.0 2.0] -+ B_array=[-2.0 -1.0 1.0 2.0] -+ area=1.0 length=1.0 input_domain=1.0e-6 -+ fraction=TRUE mode=1 -+ in_low=-1.0 in_high=1.0 hyst=0.5 -+ out_lower_limit=-1.0 out_upper_limit=1.0) -* -* -r5 1 50 100.0 -a5 (50 0) (40 45) inductor1 -.model inductor1 lcouple (num_turns=10) -* -* -*** resistors to ground *** -r1 1 0 1k -* -r10 10 0 1k -r20 20 0 1k -r30 30 0 1k -r40 40 0 1k -r50 50 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models2_swept_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models2_swept_dc.deck deleted file mode 100644 index 470d11c8..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models2_swept_dc.deck +++ /dev/null @@ -1,64 +0,0 @@ -Code Model Test - Swept DC: int, d_dt, s_xfer, core, lcouple -* -* -*** analysis type *** -.dc v1 .1 10 .5 -* -*** input sources *** -v1 1 0 DC 2 -* -* -*** integrator block *** -a1 1 10 int1 -.model int1 int (in_offset=0.0 gain=2.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 out_ic=0.0) -* -* -*** differentiator block *** -a2 1 20 d_dt1 -.model d_dt1 d_dt (out_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6) -* -* -*** s_xfer block *** -a3 1 30 filter1 -.model filter1 s_xfer (in_offset=0.0 gain=1.0 num_coeff=[1.0] -+ den_coeff=[1.0 1.414214 1.0] int_ic=[0.0 0.0] -+ denormalized_freq=1.0) -* -* -* -*** magnetic core & inductive coupling *** -v40 45 46 0.0 -a4 40 45 core1 -.model core1 core (H_array=[-2.0 -1.0 1.0 2.0] -+ B_array=[-2.0 -1.0 1.0 2.0] -+ area=1.0 length=1.0 input_domain=1.0e-6 -+ fraction=TRUE mode=1 -+ in_low=-1.0 in_high=1.0 hyst=0.5 -+ out_lower_limit=-1.0 out_upper_limit=1.0) -* -* -r5 1 50 100.0 -a5 (50 0) (40 46) inductor1 -.model inductor1 lcouple (num_turns=10) -* -* -*** resistors to ground *** -r1 1 0 1k -* -r10 10 0 1e12 -r20 20 0 1e12 -r30 30 0 1e12 -r40 40 0 1e12 -r45 45 0 1e12 -r50 50 0 1e12 -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models2_transient.deck b/Windows/spice/examples/xspice/original-examples/analog_models2_transient.deck deleted file mode 100644 index c9efac72..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models2_transient.deck +++ /dev/null @@ -1,67 +0,0 @@ -Code Model Test - Transient: int, d_dt, s_xfer, core, lcouple -* -* -*** analysis type *** -.tran .1s 10s -* -*** input sources *** -* -v1 1 0 DC PWL(0 0 10 10) -* -v2 2 0 DC PWL(0 0 0.1 0.1 0.2 0.9 0.3 1.0 10 1.0) -* -* -* -*** integrator block *** -a1 1 10 int1 -.model int1 int (in_offset=0.0 gain=2.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 out_ic=0.0) -* -* -*** differentiator block *** -a2 1 20 d_dt1 -.model d_dt1 d_dt (out_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6) -* -* -*** s_xfer block *** -a3 2 30 filter1 -.model filter1 s_xfer (in_offset=0.0 gain=1.0 num_coeff=[1.0] -+ den_coeff=[1.0 1.414214 1.0] int_ic=[0.0 0.0] -+ denormalized_freq=1.0) -* -* -* -*** magnetic core & inductive coupling *** -a4 40 45 core1 -.model core1 core (H_array=[-2.0 -1.0 1.0 2.0] -+ B_array=[-2.0 -1.0 1.0 2.0] -+ area=1.0 length=1.0 input_domain=1.0e-6 -+ fraction=TRUE mode=1 -+ in_low=-1.0 in_high=1.0 hyst=0.5 -+ out_lower_limit=-1.0 out_upper_limit=1.0) -* -* -r5 1 50 100.0 -a5 (50 0) (40 45) inductor1 -.model inductor1 lcouple (num_turns=10) -* -* -*** resistors to ground *** -r1 1 0 1k -r2 2 0 1k -* -r10 10 0 1k -r20 20 0 1k -r30 30 0 1k -r40 40 0 1k -r50 50 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models3_ac.deck b/Windows/spice/examples/xspice/original-examples/analog_models3_ac.deck deleted file mode 100644 index 3c4d7fa9..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models3_ac.deck +++ /dev/null @@ -1,81 +0,0 @@ -Code Model Test - AC: hyst, limit, ilimit, climit, cmeter, lmeter -* -* -*** analysis type *** -.ac dec 10 10 1000 -* -* -*** input sources *** -* -v1 1 0 1.0 AC 1.0 0.0 -* -v2 2 0 DC 10.0 -* -v3 3 0 DC -10.0 -* -* -* -*** hyst block *** -a1 1 10 hyst1 -.model hyst1 hyst (in_low=0.0 in_high=1.0 hyst=0.1 out_lower_limit=0.0 -+ out_upper_limit=1.0 input_domain=0.01 fraction=TRUE) -* -* -*** limit block *** -a2 1 20 limit1 -.model limit1 limit (in_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 fraction=FALSE) -* -* -*** ilimit block *** -a3 1 2 3 30 ilimit1 -.model ilimit1 ilimit (in_offset=0.0 gain=1.0 r_out_source=1.0 -+ r_out_sink=1.0 i_limit_source=1.0 -+ i_limit_sink=1.0 v_pwr_range=1.0e-3 -+ i_source_range=1.0e-6 i_sink_range=1.0e-6 -+ r_out_domain=1.0e-6) -* -* -*** climit block *** -a4 1 2 3 40 climit1 -.model climit1 climit (in_offset=0.0 gain=1.0 upper_delta=0.0 -+ lower_delta=0.0 limit_range=1.0e-6 -+ fraction=FALSE) -* -* -*** cmeter block *** -c5 51 0 1.0e-6 -a5 51 50 cmeter1 -.model cmeter1 cmeter (gain=1.0) -* -* -* -*** lmeter block *** -l6 61 0 1.0e-6 -a6 61 60 lmeter1 -.model lmeter1 lmeter (gain=1.0) -* -* -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r51 51 0 10k -r60 60 0 10k -r61 61 0 10k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models3_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models3_dc.deck deleted file mode 100644 index cff617cd..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models3_dc.deck +++ /dev/null @@ -1,79 +0,0 @@ -Code Model Test - DC: hyst, limit, ilimit, climit, cmeter, lmeter -* -* -*** analysis type *** -.op -* -*** input sources *** -v1 1 0 DC 1.0 -* -v2 2 0 DC 10.0 -* -v3 3 0 DC -10.0 -* -* -* -*** hyst block *** -a1 1 10 hyst1 -.model hyst1 hyst (in_low=0.0 in_high=1.0 hyst=0.1 out_lower_limit=0.0 -+ out_upper_limit=1.0 input_domain=0.01 fraction=TRUE) -* -* -*** limit block *** -a2 1 20 limit1 -.model limit1 limit (in_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 fraction=FALSE) -* -* -*** ilimit block *** -a3 1 2 3 30 ilimit1 -.model ilimit1 ilimit (in_offset=0.0 gain=1.0 r_out_source=1.0 -+ r_out_sink=1.0 i_limit_source=1.0 -+ i_limit_sink=1.0 v_pwr_range=1.0e-3 -+ i_source_range=1.0e-3 i_sink_range=1.0e-3 -+ r_out_domain=1.0e-3) -* -* -*** climit block *** -a4 1 2 3 40 climit1 -.model climit1 climit (in_offset=0.0 gain=1.0 upper_delta=0.0 -+ lower_delta=0.0 limit_range=1.0e-6 -+ fraction=FALSE) -* -* -*** cmeter block *** -c5 51 0 1.0e-6 -a5 51 50 cmeter1 -.model cmeter1 cmeter (gain=1.0) -* -* -* -*** lmeter block *** -l6 61 0 1.0e-6 -a6 61 60 lmeter1 -.model lmeter1 lmeter (gain=1.0) -* -* -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r51 51 0 10k -r60 60 0 10k -r61 61 0 10k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models3_swept_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models3_swept_dc.deck deleted file mode 100644 index 394e7aac..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models3_swept_dc.deck +++ /dev/null @@ -1,79 +0,0 @@ -Code Model Test - DC: hyst, limit, ilimit, climit, cmeter, lmeter -* -* -*** analysis type *** -.dc v1 .1 15 .5 -* -*** input sources *** -v1 1 0 DC 1.0 -* -v2 2 0 DC 10.0 -* -v3 3 0 DC -10.0 -* -* -* -*** hyst block *** -a1 1 10 hyst1 -.model hyst1 hyst (in_low=0.0 in_high=1.0 hyst=0.1 out_lower_limit=0.0 -+ out_upper_limit=1.0 input_domain=0.01 fraction=TRUE) -* -* -*** limit block *** -a2 1 20 limit1 -.model limit1 limit (in_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 fraction=FALSE) -* -* -*** ilimit block *** -a3 1 2 3 30 ilimit1 -.model ilimit1 ilimit (in_offset=0.0 gain=1.0 r_out_source=1.0 -+ r_out_sink=1.0 i_limit_source=1.0 -+ i_limit_sink=1.0 v_pwr_range=1.0e-3 -+ i_source_range=1.0e-6 i_sink_range=1.0e-6 -+ r_out_domain=1.0e-6) -* -* -*** climit block *** -a4 1 2 3 40 climit1 -.model climit1 climit (in_offset=0.0 gain=1.0 upper_delta=0.0 -+ lower_delta=0.0 limit_range=1.0e-6 -+ fraction=FALSE) -* -* -*** cmeter block *** -c5 51 0 1.0e-6 -a5 51 50 cmeter1 -.model cmeter1 cmeter (gain=1.0) -* -* -* -*** lmeter block *** -l6 61 0 1.0e-6 -a6 61 60 lmeter1 -.model lmeter1 lmeter (gain=1.0) -* -* -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r51 51 0 10k -r60 60 0 10k -r61 61 0 10k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models3_transient.deck b/Windows/spice/examples/xspice/original-examples/analog_models3_transient.deck deleted file mode 100644 index c92ffff9..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models3_transient.deck +++ /dev/null @@ -1,80 +0,0 @@ -Code Model Test - Transient: hyst, limit, ilimit, climit, cmeter, lmeter -* -* -*** analysis type *** -.tran .1s 15s -* -*** input sources *** -* -v1 1 0 DC PWL(0 0 15 15) -* -v2 2 0 DC 10.0 -* -v3 3 0 DC -10.0 -* -* -* -*** hyst block *** -a1 1 10 hyst1 -.model hyst1 hyst (in_low=0.0 in_high=1.0 hyst=0.1 out_lower_limit=0.0 -+ out_upper_limit=1.0 input_domain=0.01 fraction=TRUE) -* -* -*** limit block *** -a2 1 20 limit1 -.model limit1 limit (in_offset=0.0 gain=1.0 out_lower_limit=-1.0e6 -+ out_upper_limit=1.0e6 limit_range=1.0e-6 fraction=FALSE) -* -* -*** ilimit block *** -a3 1 2 3 30 ilimit1 -.model ilimit1 ilimit (in_offset=0.0 gain=1.0 r_out_source=1.0 -+ r_out_sink=1.0 i_limit_source=1.0 -+ i_limit_sink=1.0 v_pwr_range=1.0e-3 -+ i_source_range=1.0e-6 i_sink_range=1.0e-6 -+ r_out_domain=1.0e-6) -* -* -*** climit block *** -a4 1 2 3 40 climit1 -.model climit1 climit (in_offset=0.0 gain=1.0 upper_delta=0.0 -+ lower_delta=0.0 limit_range=1.0e-6 -+ fraction=FALSE) -* -* -*** cmeter block *** -c5 51 0 1.0e-6 -a5 51 50 cmeter1 -.model cmeter1 cmeter (gain=1.0) -* -* -* -*** lmeter block *** -l6 61 0 1.0e-6 -a6 61 60 lmeter1 -.model lmeter1 lmeter (gain=1.0) -* -* -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r51 51 0 10k -r60 60 0 10k -r61 61 0 10k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models4_ac.deck b/Windows/spice/examples/xspice/original-examples/analog_models4_ac.deck deleted file mode 100644 index 70413e1a..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models4_ac.deck +++ /dev/null @@ -1,78 +0,0 @@ -Code Model Test - DC: sine, triangle, aswitch, zener, oneshot -* -* -*** analysis type *** -.ac dec 10 10 1000 -* -* -*** input sources *** -* -v1 1 0 1.0 AC 1.0 0.0 -* -v2 2 0 DC 1.0 -* -v3 3 0 DC 1.0 -* -* -* -* -*** sine block *** -a1 1 10 sine1 -.model sine1 sine (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[1.0 1.0 100.0 100.0] -+ out_low=-1.0 out_high=1.0) -* -* -*** triangle block *** -a2 1 20 triangle1 -.model triangle1 triangle (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[1.0 1.0 100.0 100.0] -+ out_low=-1.0 out_high=1.0 duty_cycle=0.8) -* -* -*** aswitch block *** -a3 1 (2 30) aswitch1 -.model aswitch1 aswitch (cntl_off=0.0 cntl_on=1.0 log=TRUE -+ r_off=1.0e12 r_on=10.0) -* -* -*** zener diode *** -r4 1 40 10K -a4 (40 0) zener1 -.model zener1 zener (v_breakdown=10.0 i_breakdown=2.0e-2 -+ r_breakdown=1.0 i_rev=1.0e-6 i_sat=1.0e-12 -+ n_forward=1.0 limit_switch=FALSE) -* -* -*** oneshot block *** -a5 3 1 2 50 oneshot1 -.model oneshot1 oneshot (cntl_array=[-1.0 0.0 1.0 2.0] -+ pw_array=[1.0 1.0 0.1 0.1] clk_trig=0.5 -+ pos_edge_trig=TRUE out_low=0.0 out_high=1.0 -+ rise_time=1.0e-6 rise_delay=1.0e-9 -+ fall_delay=1.0e-9 fall_time=1.0e-6 -+ retrig=FALSE) -* -* -* -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r60 60 0 10k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models4_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models4_dc.deck deleted file mode 100644 index b3254ea5..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models4_dc.deck +++ /dev/null @@ -1,74 +0,0 @@ -Code Model Test - DC: sine triangle aswitch zener oneshot -* -* -*** analysis type *** -.op -* -*** input sources *** -v1 1 0 DC 1.0 -* -v2 2 0 DC 1.0 -* -v3 3 0 DC 1.0 -* -* -*** sine block *** -a1 1 10 sine1 -.model sine1 sine (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[1.0 1.0 100.0 100.0] -+ out_low=-1.0 out_high=1.0) -* -* -*** triangle block *** -a2 1 20 triangle1 -.model triangle1 triangle (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[1.0 1.0 100.0 100.0] -+ out_low=-1.0 out_high=1.0 duty_cycle=0.8) -* -* -*** aswitch block *** -a3 1 (2 30) aswitch1 -.model aswitch1 aswitch (cntl_off=0.0 cntl_on=1.0 log=TRUE -+ r_off=1.0e12 r_on=10.0) -* -* -*** zener diode *** -r4 1 40 10K -a4 (40 0) zener1 -.model zener1 zener (v_breakdown=10.0 i_breakdown=2.0e-2 -+ r_breakdown=1.0 i_rev=1.0e-6 i_sat=1.0e-12 -+ n_forward=1.0 limit_switch=FALSE) -* -* -*** oneshot block *** -a5 3 1 2 50 oneshot1 -.model oneshot1 oneshot (cntl_array=[-1.0 0.0 1.0 2.0] -+ pw_array=[1.0 1.0 0.1 0.1] clk_trig=0.5 -+ pos_edge_trig=TRUE out_low=0.0 out_high=1.0 -+ rise_time=1.0e-6 rise_delay=1.0e-9 -+ fall_delay=1.0e-9 fall_time=1.0e-6 -+ retrig=FALSE) -* -* -* -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r60 60 0 10k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models4_swept_dc.deck b/Windows/spice/examples/xspice/original-examples/analog_models4_swept_dc.deck deleted file mode 100644 index d06fe05f..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models4_swept_dc.deck +++ /dev/null @@ -1,72 +0,0 @@ -Code Model Test - Swept DC: sine, triangle, aswitch, zener, oneshot -* -* -*** analysis type *** -.dc v1 .1 15 .5 -* -*** input sources *** -v1 1 0 DC 1.0 -* -v2 2 0 DC 1.0 -* -v3 3 0 DC 1.0 -* -* -*** sine block *** -a1 1 10 sine1 -.model sine1 sine (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[1.0 1.0 100.0 100.0] -+ out_low=-1.0 out_high=1.0) -* -* -*** triangle block *** -a2 1 20 triangle1 -.model triangle1 triangle (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[1.0 1.0 100.0 100.0] -+ out_low=-1.0 out_high=1.0 duty_cycle=0.8) -* -* -*** aswitch block *** -a3 1 (2 30) aswitch1 -.model aswitch1 aswitch (cntl_off=0.0 cntl_on=1.0 log=TRUE -+ r_off=1.0e12 r_on=10.0) -* -* -*** zener diode *** -r4 1 40 100 -a4 (0 40) zener1 -.model zener1 zener (v_breakdown=8.0 i_breakdown=2.0e-2 -+ r_breakdown=1.0 i_rev=1.0e-6 i_sat=1.0e-12 -+ n_forward=1.0 limit_switch=FALSE) -* -* -*** oneshot block *** -a5 3 1 2 50 oneshot1 -.model oneshot1 oneshot (cntl_array=[-1.0 0.0 1.0 2.0] -+ pw_array=[1.0 1.0 0.1 0.1] clk_trig=0.5 -+ pos_edge_trig=TRUE out_low=0.0 out_high=1.0 -+ rise_time=1.0e-6 rise_delay=1.0e-9 -+ fall_delay=1.0e-9 fall_time=1.0e-6 -+ retrig=FALSE) -* -* -* -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r60 60 0 10k -* -* -.end - - - - diff --git a/Windows/spice/examples/xspice/original-examples/analog_models4_transient.deck b/Windows/spice/examples/xspice/original-examples/analog_models4_transient.deck deleted file mode 100644 index a5bc2687..00000000 --- a/Windows/spice/examples/xspice/original-examples/analog_models4_transient.deck +++ /dev/null @@ -1,81 +0,0 @@ -Code Model Test - Transient: sine, triangle, aswitch, zener, oneshot -* -* -*** analysis type *** -.tran .01ms 2ms -* -*** input sources *** -* -v1 1 0 DC 0.0 PWL(0 0 2e-3 2) -* -v2 2 0 DC 0.0 PWL(0 0 2e-3 10) -* -v3 3 0 DC 0.0 PWL(0 0.0 0.9e-3 0.0 1e-3 1.0 1.9e-3 1.0 2e-3 0.0 2.9e-3 0.0) -* -v4 4 0 DC 1.0 -* -* -*** sine block *** -a1 2 10 sine1 -.model sine1 sine (cntl_array=[-1.0 0.0 10.0 20.0] -+ freq_array=[500 500 2000 2000] -+ out_low=-1.0 out_high=1.0) -* -* -*** triangle block *** -a2 1 20 triangle1 -.model triangle1 triangle (cntl_array=[-1.0 0.0 10.0 20.0] -+ freq_array=[500 500 10000 10000] -+ out_low=-1.0 out_high=1.0 duty_cycle=0.5) -* -* -*** aswitch block *** -a3 1 (4 30) aswitch1 -.model aswitch1 aswitch (cntl_off=0.0 cntl_on=1.0 log=TRUE -+ r_off=1.0e12 r_on=10.0) -* -* -*** zener diode *** -rzener 2 40 100 -a4 (0 40) zener1 -.model zener1 zener (v_breakdown=9.0 i_breakdown=2.0e-2 -+ r_breakdown=1.0 i_rev=1.0e-6 i_sat=1.0e-12 -+ n_forward=1.0 limit_switch=FALSE) -* -* -*** oneshot block *** -a5 3 1 0 50 oneshot1 -.model oneshot1 oneshot (cntl_array=[-1.0 0.0 1.0 2.0] -+ pw_array=[2.0e-3 2.0e-3 0.1e-3 0.1e-3] clk_trig=0.5 -+ pos_edge_trig=TRUE out_low=0.0 out_high=1.0 -+ rise_time=1.0e-6 rise_delay=1.0e-9 -+ fall_delay=1.0e-9 fall_time=1.0e-6 -+ retrig=FALSE) -* -* -*** square block *** -a6 2 60 square1 -.model square1 square (cntl_array=[-1.0 0.0 10.0 20.0] -+ freq_array=[500 500 7000 7000] -+ out_low=-0.8 out_high=1.2 duty_cycle=0.5 -+ rise_time=1e-6 fall_time=2e-6) -* -*** resistors to ground *** -r1 1 0 10k -r2 2 0 10k -r3 3 0 10k -r4 4 0 10k -* -r10 10 0 10k -r20 20 0 10k -r30 30 0 10k -r40 40 0 10k -r50 50 0 10k -r60 60 0 10k -* -* -.end - - - - diff --git a/Windows/spice/examples/xspice/original-examples/arbitrary_phase.deck b/Windows/spice/examples/xspice/original-examples/arbitrary_phase.deck deleted file mode 100644 index 3ef68bc2..00000000 --- a/Windows/spice/examples/xspice/original-examples/arbitrary_phase.deck +++ /dev/null @@ -1,17 +0,0 @@ -Arbitrary Phase SIN and PULSE Sources -* -* This circuit generates two cycles of sine and square waves -* beginning at +45 degrees. -* -* Phase shift is specified after Berkeley defined parameters -* on the independent source cards. -* -.tran 2e-5 2e-3 -* -v1 1 0 0.0 sin(0 1 1k 0 0 45.0) -r1 1 0 1k -* -v2 2 0 0.0 pulse(-1 1 0 1e-5 1e-5 5e-4 1e-3 45.0) -r2 2 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/bad_io.deck b/Windows/spice/examples/xspice/original-examples/bad_io.deck deleted file mode 100644 index 74678115..00000000 --- a/Windows/spice/examples/xspice/original-examples/bad_io.deck +++ /dev/null @@ -1,17 +0,0 @@ -Invalid number of inputs/outputs -* -* This circuit contains a simple gain block to demonstrate -* that the simulator reports an error if the number of -* connections on the code model is incorrect. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -a1 1 2 3 gain_block -a2 1 gain_block -.model gain_block gain (gain=10) -r2 2 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/bad_io_type.deck b/Windows/spice/examples/xspice/original-examples/bad_io_type.deck deleted file mode 100644 index 41e64ad5..00000000 --- a/Windows/spice/examples/xspice/original-examples/bad_io_type.deck +++ /dev/null @@ -1,25 +0,0 @@ -Invalid input/output type -* -* This circuit contains a simple gain block to demonstrate -* that the simulator reports an error if an invalid type -* is used with the code model connections. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -* Both connections on the gain block must be analog, but -* the second is specified as digital -* -a1 1 %d 2 gain_block -.model gain_block gain (gain=10) -r2 2 0 1k -* -* Node 1 below should be a digital node, but is an analog node -* -a2 [1] [3] dac -.model dac dac_bridge -r3 3 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/bad_name.deck b/Windows/spice/examples/xspice/original-examples/bad_name.deck deleted file mode 100644 index 0380cac2..00000000 --- a/Windows/spice/examples/xspice/original-examples/bad_name.deck +++ /dev/null @@ -1,16 +0,0 @@ -Unknown code model name -* -* This circuit contains a simple gain block to demonstrate -* that the simulator reports an error if the code model name -* is incorrect. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -a1 1 2 gain_block -.model gain_block this_model_doesnt_exist (gain=10) -r2 2 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/bad_param.deck b/Windows/spice/examples/xspice/original-examples/bad_param.deck deleted file mode 100644 index 22a2aa2f..00000000 --- a/Windows/spice/examples/xspice/original-examples/bad_param.deck +++ /dev/null @@ -1,16 +0,0 @@ -Unknown code model parameter -* -* This circuit contains a simple gain block to demonstrate -* that the simulator reports an error if the .model card -* references a parameter that doesn't exist -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -a1 1 2 gain_block -.model gain_block gain (this_parameter_doesnt_exist=2 gain=10) -r2 2 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/bad_param_type.deck b/Windows/spice/examples/xspice/original-examples/bad_param_type.deck deleted file mode 100644 index f110feda..00000000 --- a/Windows/spice/examples/xspice/original-examples/bad_param_type.deck +++ /dev/null @@ -1,16 +0,0 @@ -Invalid parameter type -* -* This circuit contains a simple gain block to demonstrate -* that the simulator reports an error if the parameter value -* is invalid. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -a1 1 2 gain_block -.model gain_block gain (gain=false) -r2 2 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/diffpair.in b/Windows/spice/examples/xspice/original-examples/diffpair.in deleted file mode 100644 index da321ce8..00000000 --- a/Windows/spice/examples/xspice/original-examples/diffpair.in +++ /dev/null @@ -1,28 +0,0 @@ -difpair ckt - simple differential pair -*.width in=72 -.opt acct list node lvlcod=2 -*.tf v(5) vin -*.dc vin -0.25 0.25 0.005 -*.ac dec 10 1 10ghz -.tran 5ns 500ns -vin 1 0 sin(0 0.1 5meg) ac 1 -vcc 8 0 12 -vee 9 0 -12 -q1 4 2 6 qnl -q2 5 3 6 qnl -rs1 1 2 1k -rs2 3 0 1k -rc1 4 8 10k -rc2 5 8 10k -q3 6 7 9 qnl -q4 7 7 9 qnl -rbias 7 8 20k -.model qnl npn(bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf cjc=2pf -+ va=50) -.print dc v(4) v(5) -.plot dc v(5) -.print ac vm(5) vp(5) -.plot ac vm(5) vp(5) -.print tran v(4) v(5) -.plot tran v(5) -.end diff --git a/Windows/spice/examples/xspice/original-examples/digital_invert.deck b/Windows/spice/examples/xspice/original-examples/digital_invert.deck deleted file mode 100644 index 08d7f6e9..00000000 --- a/Windows/spice/examples/xspice/original-examples/digital_invert.deck +++ /dev/null @@ -1,23 +0,0 @@ -Digital inversions -* -.tran 1e-8 1e-6 -* -v1 1 0 0.0 pulse(0 1 0 1e-8 1e-8 0.25e-6 0.5e-6) -r1 1 0 1k -* -a1 [1] [2] adc -.model adc adc_bridge -* -a2 2 3 inv -a3 2 ~4 inv -a4 ~2 5 inv -a5 ~2 ~6 inv -.model inv d_inverter -* -a6 [2 ~4] 7 nand -.model nand d_nand -* -a8 [2 3 4 5 6 7] [12 13 14 15 16 17] dac -.model dac dac_bridge -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/digital_models.deck b/Windows/spice/examples/xspice/original-examples/digital_models.deck deleted file mode 100644 index 39f73727..00000000 --- a/Windows/spice/examples/xspice/original-examples/digital_models.deck +++ /dev/null @@ -1,20 +0,0 @@ -Digital models -* -* This circuit contains a nand gate oscillator enabled by -* a pulse input after 20nS. Node 1 is an analog node. -* Nodes 2 and 3 are digital nodes. -* -.tran 1e-8 1e-7 -* -v1 1 0 0.0 pulse(0 1 2e-8 1e-9 1e-9) -* -r1 1 0 1k -* -a1 [1] [2] atod1 -.model atod1 adc_bridge (in_low=0.25 in_high=0.75 -+ rise_delay=1e-9 fall_delay=1e-9) -* -a2 [2 3] 3 nand -.model nand d_nand (rise_delay=1e-9 fall_delay=1e-9) -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/digital_models1.deck b/Windows/spice/examples/xspice/original-examples/digital_models1.deck deleted file mode 100644 index c78fa45a..00000000 --- a/Windows/spice/examples/xspice/original-examples/digital_models1.deck +++ /dev/null @@ -1,77 +0,0 @@ -Code Model Test: buffer, inverter, and, nand, or, nor, xor, xnor -* -* -*** analysis type *** -.tran .01s 4s -* -*** input sources *** -* -v2 200 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) ) -* -v1 100 0 DC PWL( (0 0.0) (1.0 0.0) (1.0000000001 1.0) (2 1.0) -+ (2.0000000001 0.0) (3 0.0) (3.0000000001 1.0) (4 1.0) ) -* -* -*** adc_bridge blocks *** -aconverter [200 100] [2 1] adc_bridge1 -.model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9 -+ rise_delay=1.0e-12 fall_delay=1.0e-12) -* -* -* -*** buffer block *** -a1 1 10 d_buffer1 -.model d_buffer1 d_buffer (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -*** inverter block *** -a2 1 20 d_inv1 -.model d_inv1 d_inverter (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -*** and block *** -a3 [1 2] 30 d_and1 -.model d_and1 d_and (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -*** nand block *** -a4 [1 2] 40 d_nand1 -.model d_nand1 d_nand (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -*** or block *** -a5 [1 2] 50 d_or1 -.model d_or1 d_or (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -*** nor block *** -a6 [1 2] 60 d_nor1 -.model d_nor1 d_nor (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -*** xor block *** -a7 [1 2] 70 d_xor1 -.model d_xor1 d_xor (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -*** xnor block *** -a8 [1 2] 80 d_xnor1 -.model d_xnor1 d_xnor (rise_delay=1.0e-6 fall_delay=2.0e-6 -+ input_load=1.0e-12) -* -* -* -*** resistors to ground *** -r1 100 0 1k -r2 200 0 1k -* -* -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/digital_models2.deck b/Windows/spice/examples/xspice/original-examples/digital_models2.deck deleted file mode 100644 index 9f624407..00000000 --- a/Windows/spice/examples/xspice/original-examples/digital_models2.deck +++ /dev/null @@ -1,91 +0,0 @@ -Code Model Test: d flip-flop, jk flip-flop, toggle ff, set-reset ff -* -* -*** analysis type *** -.tran .01s 4s -* -*** input sources *** -* -vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) ) -* -* -vdata2 200 0 DC PWL( (0 0.0) (1.0 0.0) (1.0000000001 1.0) (2 1.0) -+ (2.0000000001 0.0) (3 0.0) (3.0000000001 1.0) (4 1.0) ) -* -* -vclk 300 0 DC PWL( (0 0.0) (0.5 0.0) (0.50000000001 1.0) -+ (1.0 1.0) (1.00000000001 0.0) -+ (1.5 0.0) (1.50000000001 1.0) -+ (2.0 1.0) (2.00000000001 0.0) -+ (2.5 0.0) (2.50000000001 1.0) -+ (3.0 1.0) (3.00000000001 0.0) -+ (3.5 0.0) (3.50000000001 1.0) (4.0 1.0) ) -* -* -vset 400 0 DC 0.0 -* -* -vreset 500 0 DC PWL( (0 0.0) (3.8 0.0) (3.80000000001 1.0) (4 1.0) ) -* -* -*** adc_bridge blocks *** -aconverter [100 200 300 400 500] [1 2 3 4 5] adc_bridge1 -.model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9 -+ rise_delay=1.0e-12 fall_delay=1.0e-12) -* -* -* -*** d flip-flop block *** -a1 1 3 4 5 10 11 d_dff1 -.model d_dff1 d_dff (clk_delay=1.0e-6 set_delay=2.0e-6 -+ reset_delay=3.0e-6 ic=0 -+ rise_delay=4.0e-6 fall_delay=5.0e-6 -+ data_load=1.0e-12 clk_load=1.0e-12 -+ set_load=1.0e-12 reset_load=1.0e-12) -* -* -*** jk flip-flop block *** -a2 1 2 3 4 5 20 21 d_jkff1 -.model d_jkff1 d_jkff (clk_delay=1.0e-6 set_delay=2.0e-6 -+ reset_delay=3.0e-6 ic=0 -+ rise_delay=4.0e-6 fall_delay=5.0e-6 -+ jk_load=1.0e-12 clk_load=1.0e-12 -+ set_load=1.0e-12 reset_load=1.0e-12) -* -* -*** toggle flip-flop block *** -a3 1 3 4 5 30 31 d_tff1 -.model d_tff1 d_tff (clk_delay=1.0e-6 set_delay=2.0e-6 -+ reset_delay=3.0e-6 ic=0 -+ rise_delay=4.0e-6 fall_delay=5.0e-6 -+ t_load=1.0e-12 clk_load=1.0e-12 -+ set_load=1.0e-12 reset_load=1.0e-12) -* -* -*** set-reset flip-flop block *** -a4 1 2 3 4 5 40 41 d_srff1 -.model d_srff1 d_srff (clk_delay=1.0e-6 set_delay=2.0e-6 -+ reset_delay=3.0e-6 ic=0 -+ rise_delay=4.0e-6 fall_delay=5.0e-6 -+ sr_load=1.0e-12 clk_load=1.0e-12 -+ set_load=1.0e-12 reset_load=1.0e-12) -* -* -* -* -*** resistors to ground *** -r1 100 0 1k -r2 200 0 1k -r3 300 0 1k -r4 400 0 1k -r5 500 0 1k -* -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/digital_models3.deck b/Windows/spice/examples/xspice/original-examples/digital_models3.deck deleted file mode 100644 index 476ed307..00000000 --- a/Windows/spice/examples/xspice/original-examples/digital_models3.deck +++ /dev/null @@ -1,92 +0,0 @@ -Code Model Test: d latch, set-reset latch, frequency divider -* -* -*** analysis type *** -.tran .01s 8s -* -*** input sources *** -* -vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) ) -* -* -vdata2 200 0 DC PWL( (0 0.0) (1.0 0.0) (1.0000000001 1.0) (2 1.0) -+ (2.0000000001 0.0) (3 0.0) (3.0000000001 1.0) (4 1.0) ) -* -* -vclk 300 0 DC PWL( (0 0.0) (0.5 0.0) (0.50000000001 1.0) -+ (1.0 1.0) (1.00000000001 0.0) -+ (1.5 0.0) (1.50000000001 1.0) -+ (2.0 1.0) (2.00000000001 0.0) -+ (2.5 0.0) (2.50000000001 1.0) -+ (3.0 1.0) (3.00000000001 0.0) -+ (3.5 0.0) (3.50000000001 1.0) -+ (4.0 1.0) (4.00000000001 0.0) -+ (4.5 0.0) (4.50000000001 1.0) -+ (5.0 1.0) (5.00000000001 0.0) -+ (5.5 0.0) (5.50000000001 1.0) -+ (6.0 1.0) (6.00000000001 0.0) -+ (6.5 0.0) (6.50000000001 1.0) -+ (7.0 1.0) (7.00000000001 0.0) -+ (7.5 0.0) (7.50000000001 1.0) (8.0 1.0) ) -* -* -vset 400 0 DC 0.0 -* -* -vreset 500 0 DC PWL( (0 0.0) (3.8 0.0) (3.80000000001 1.0) (4 1.0) ) -* -* -*** adc_bridge block *** -aconverter [100 200 300 400 500] [1 2 3 4 5] adc_bridge1 -.model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9 -+ rise_delay=1.0e-12 fall_delay=1.0e-12) -* -* -* -*** d latch block *** -a1 1 3 4 5 10 11 d_dlatch1 -.model d_dlatch1 d_dlatch (data_delay=1.0e-6 enable_delay=2.0e-6 -+ set_delay=3.0e-6 reset_delay=4.0e-6 -+ ic=0 -+ rise_delay=5.0e-6 fall_delay=6.0e-6 -+ data_load=1.0e-12 enable_load=1.0e-12 -+ set_load=1.0e-12 reset_load=1.0e-12) -* -* -*** set-reset latch block *** -a2 1 2 3 4 5 20 21 d_srlatch1 -.model d_srlatch1 d_srlatch (sr_delay=1.0e-6 enable_delay=2.0e-6 -+ set_delay=3.0e-6 reset_delay=4.0e-6 -+ ic=0 -+ rise_delay=5.0e-6 fall_delay=6.0e-6 -+ sr_load=1.0e-12 enable_load=1.0e-12 -+ set_load=1.0e-12 reset_load=1.0e-12) -* -* -*** frequency divider block *** -a3 3 30 d_fdiv1 -.model d_fdiv1 d_fdiv (div_factor=3 high_cycles=2 -+ i_count=0 rise_delay=1.0e-6 fall_delay=2.0e-6 -+ freq_in_load=1.0e-12) -* -* -* -* -* -* -*** resistors to ground *** -r1 100 0 1k -r2 200 0 1k -r3 300 0 1k -r4 400 0 1k -r5 500 0 1k -* -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/digital_models4.deck b/Windows/spice/examples/xspice/original-examples/digital_models4.deck deleted file mode 100644 index 6d18c98b..00000000 --- a/Windows/spice/examples/xspice/original-examples/digital_models4.deck +++ /dev/null @@ -1,91 +0,0 @@ -Code Model Test: State Machine, RAM -* -* -*** analysis type *** -.tran .01s 8s -* -*** input sources *** -* -vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) -+ (3.5000000001 0.0) (4 0.0) ) -* -* -vdata2 200 0 DC PWL( (0 0.0) (1.0 0.0) (1.0000000001 1.0) (2 1.0) -+ (2.0000000001 0.0) (3 0.0) (3.0000000001 1.0) (4 1.0) ) -* -* -vclk 300 0 DC PWL( (0 0.0) (0.5 0.0) (0.50000000001 1.0) -+ (1.0 1.0) (1.00000000001 0.0) -+ (1.5 0.0) (1.50000000001 1.0) -+ (2.0 1.0) (2.00000000001 0.0) -+ (2.5 0.0) (2.50000000001 1.0) -+ (3.0 1.0) (3.00000000001 0.0) -+ (3.5 0.0) (3.50000000001 1.0) -+ (4.0 1.0) (4.00000000001 0.0) -+ (4.5 0.0) (4.50000000001 1.0) -+ (5.0 1.0) (5.00000000001 0.0) -+ (5.5 0.0) (5.50000000001 1.0) -+ (6.0 1.0) (6.00000000001 0.0) -+ (6.5 0.0) (6.50000000001 1.0) -+ (7.0 1.0) (7.00000000001 0.0) -+ (7.5 0.0) (7.50000000001 1.0) (8.0 1.0) ) -* -vaddr1 400 0 DC 0 -* -* -vaddr2 500 0 DC PWL( (0 0.0) (0.6 0.0) (0.60000000001 1.0) -+ (0.9 1.0) (0.90000000001 0.0) -+ (2.6 0.0) (2.60000000001 1.0) -+ (2.9 1.0) (2.90000000001 0.0) (3.0 0.0) ) -* -* -* -vselect 600 0 DC PWL( (0 0.0) (1.0 0.0) (2 1.0) (2.0000000001 1.0) ) -* -* -* -* -* -*** adc_bridge block *** -aconverter [100 200 300 400 500 600] [1 2 3 4 5 6] adc_bridge1 -.model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9 -+ rise_delay=1.0e-12 fall_delay=1.0e-12) -* -* -* -*** state machine block *** -*a1 [1 2] 3 4 [10 11] d_state1 -*.model d_state1 d_state (clk_delay=1.0e-6 reset_delay=2.0e-6 -*+ state_file="state.txt" reset_state=0 -*+ input_load=1.0e-12 clk_load=1.0e-12 -*+ reset_load=1.0e-12) -* -* -*** RAM block *** -a2 [1 2] [20 21] [3 4] 5 [6] d_ram1 -.model d_ram1 d_ram (select_value=1 ic=0 -+ read_delay=1.0e-6 data_load=1.0e-12 -+ address_load=1.0e-12 select_load=1.0e-12 -+ enable_load=1.0e-12) -* -* -* -* -* -*** resistors to ground *** -r1 100 0 10k -r2 200 0 10k -r3 300 0 10k -r4 400 0 10k -r5 500 0 10k -r6 600 0 10k -* -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/dot_model_ref.deck b/Windows/spice/examples/xspice/original-examples/dot_model_ref.deck deleted file mode 100644 index 159d144f..00000000 --- a/Windows/spice/examples/xspice/original-examples/dot_model_ref.deck +++ /dev/null @@ -1,19 +0,0 @@ -Model card reference -* -* This circuit contains simple gain blocks that share a -* single .model card. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -a1 1 2 gain_block -r2 2 0 1k -* -a2 1 3 gain_block -r3 3 0 1k -* -.model gain_block gain (in_offset = 1 gain=10) -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/hybrid_models1_dc.deck b/Windows/spice/examples/xspice/original-examples/hybrid_models1_dc.deck deleted file mode 100644 index 837b8baa..00000000 --- a/Windows/spice/examples/xspice/original-examples/hybrid_models1_dc.deck +++ /dev/null @@ -1,46 +0,0 @@ -Code Model Test - DC: d_osc, dac_bridge, adc_bridge -* -* -*** analysis type *** -.op -* -*** input sources *** -v1 1 0 DC 2 -* -v2 2 0 DC 2 -* -*** d_osc block *** -a1 1 10 d_osc1 -.model d_osc1 d_osc (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[100 100 1000 1000] -+ duty_cycle=0.5 init_phase=0.0 -+ rise_delay=1.0e-6 fall_delay=2.0e-6) -* -*** dac_bridge block *** -a2 [10] [20] dac_bridge1 -.model dac_bridge1 dac_bridge (out_low=0.5 out_high=4.5 out_undef=1.8 -+ input_load=1.0e-12 -+ t_rise=1.0e-6 t_fall=2.0e-6) -* -* -*** adc_bridge block *** -a3 [2] [30] adc_bridge1 -.model adc_bridge1 adc_bridge (in_low=0.7 in_high=2.4 -+ rise_delay=1.0e-12 fall_delay=2.0e-12) -* -* -* -*** resistors to ground *** -r1 1 0 1k -r2 2 0 1k -* -r20 20 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/hybrid_models1_transient.deck b/Windows/spice/examples/xspice/original-examples/hybrid_models1_transient.deck deleted file mode 100644 index e09b15ad..00000000 --- a/Windows/spice/examples/xspice/original-examples/hybrid_models1_transient.deck +++ /dev/null @@ -1,48 +0,0 @@ -Code Model Test - Transient: d_osc, dac_bridge, adc_bridge -* -* -*** analysis type *** -.tran .01s 1s -* -*** input sources *** -* -v1 1 0 DC PWL( (0 0.0) (1 1.0) ) -* -v2 2 0 DC PWL( (0 0.0) (1 5.0) ) -* -* -*** d_osc block *** -a1 1 10 d_osc1 -.model d_osc1 d_osc (cntl_array=[-1.0 0.0 1.0 2.0] -+ freq_array=[1.0 1.0 8.0 8.0] -+ duty_cycle=0.5 init_phase=0.0 -+ rise_delay=1.0e-6 fall_delay=2.0e-6) -* -*** dac_bridge block *** -a2 [10] [20] dac_bridge1 -.model dac_bridge1 dac_bridge (out_low=0.5 out_high=4.5 out_undef=1.8 -+ input_load=1.0e-12 -+ t_rise=1.0e-6 t_fall=2.0e-6) -* -* -*** adc_bridge block *** -a3 [2] [30] adc_bridge1 -.model adc_bridge1 adc_bridge (in_low=0.7 in_high=2.4 -+ rise_delay=1.0e-12 fall_delay=2.0e-12) -* -* -* -*** resistors to ground *** -r1 1 0 1k -r2 2 0 1k -* -r20 20 0 1k -* -* -.end - - - - - - diff --git a/Windows/spice/examples/xspice/original-examples/initial_conditions.deck b/Windows/spice/examples/xspice/original-examples/initial_conditions.deck deleted file mode 100644 index f2ca5d9f..00000000 --- a/Windows/spice/examples/xspice/original-examples/initial_conditions.deck +++ /dev/null @@ -1,19 +0,0 @@ -Capacitor and inductor with natural initial conditions -* -* This circuit contains a capacitor and an inductor with -* initial conditions on them. Each of the components -* has a parallel resistor so that an exponential decay -* of the initial condition occurs with a time constant of -* 1 second. -* -.tran 0.1 5 -* -a1 1 0 cap -.model cap capacitor (c=1000uf ic=1) -r1 1 0 1k -* -a2 2 0 ind -.model ind inductor (l=1H ic=1) -r2 2 0 1.0 -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/io_ordering.deck b/Windows/spice/examples/xspice/original-examples/io_ordering.deck deleted file mode 100644 index dea8459c..00000000 --- a/Windows/spice/examples/xspice/original-examples/io_ordering.deck +++ /dev/null @@ -1,17 +0,0 @@ -IO ordering -* -* This circuit contains a simple gain block. The order of -* the nodes listed on the instance line follows the order -* of the connections defined in the 'ifspec.ifs' file for -* the model. Refer to /atesse-su/src/cml/gain/ifspec.ifs . -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -a1 1 2 gain_block -.model gain_block gain (gain=10) -r2 2 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/io_types.deck b/Windows/spice/examples/xspice/original-examples/io_types.deck deleted file mode 100644 index 4a55a491..00000000 --- a/Windows/spice/examples/xspice/original-examples/io_types.deck +++ /dev/null @@ -1,34 +0,0 @@ -IO types -* -* This circuit contains a mix of input output types including -* voltages, currents, digital signals, and user defined -* signals. -* -.tran 1e-6 1e-4 -* -v1 1 0 0.0 pulse(0 1 2e-5) -r1 1 0 1k -* -abridge1 [1] [enable] node_bridge1 -.model node_bridge1 adc_bridge -* -aclk [enable clk] clk nand -.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5) -* -abridge2 clk enable real_node1 node_bridge2 -.model node_bridge2 d_to_real (zero=-1 one=1) -* -again real_node1 real_node2 times10 -.model times10 real_gain (gain=10) -* -abridge3 real_node2 analog_node node_bridge3 -.model node_bridge3 real_to_v -* -rout analog_node 0 1k -* -again2 %vnam v1 %i i_out gain_block -.model gain_block gain (gain=10) -ri_out i_out 0 1k -* -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/long_names.deck b/Windows/spice/examples/xspice/original-examples/long_names.deck deleted file mode 100644 index fda6613f..00000000 --- a/Windows/spice/examples/xspice/original-examples/long_names.deck +++ /dev/null @@ -1,19 +0,0 @@ -Long names -* -* This circuit contains a sine wave source followed by a -* gain block code model with a gain of 10. Long names -* are used for instances, models, and nodes. -* -.tran 1e-5 1e-3 -* -v1_123456789_123456789_1234 1 0 0.0 sin(0 1 2k) -* -r1_123456789_123456789_1234 1 0 1k -* -a1_123456789_123456789_1234 1 out_123456789_123456789_1234 -+ gain_block_123456789_123456789_1234 -* -.model gain_block_123456789_123456789_1234 gain (gain=10) -r2_123456789_123456789_1234 out_123456789_123456789_1234 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/mixed_case.deck b/Windows/spice/examples/xspice/original-examples/mixed_case.deck deleted file mode 100644 index be044c7e..00000000 --- a/Windows/spice/examples/xspice/original-examples/mixed_case.deck +++ /dev/null @@ -1,15 +0,0 @@ -MiXeD CaSe -* -* This circuit contains a simple gain block to demonstrate -* that the simulator deck parsing code is case-insensitive. -* -.TrAn 1E-5 1e-3 -* -V1 1 0 0.0 sIn(0 1 1k) -r1 1 0 1k -* -A1 1 2 GaIn_BlOcK -.MODel gAiN_bLoCk GAin (gaIN=10) -r2 2 0 1K -* -.eNd diff --git a/Windows/spice/examples/xspice/original-examples/mixed_io_size.deck b/Windows/spice/examples/xspice/original-examples/mixed_io_size.deck deleted file mode 100644 index cc6bee56..00000000 --- a/Windows/spice/examples/xspice/original-examples/mixed_io_size.deck +++ /dev/null @@ -1,33 +0,0 @@ -Mixed IO sizes -* -* This circuit contains a collection of digital and analog -* models with saclar and vector inputs of varying sizes. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 pulse(0 1 1e-4) -r1 1 0 1k -* -v2 2 0 0.0 sin(0 1 2k) -r2 2 0 1k -* -abridge1 [1] [enable] atod -.model atod adc_bridge -* -aosc [enable clk] clk nand -.model nand d_nand (rise_delay=1e-4 fall_delay=1e-4) -* -ainv clk clk_bar inv -.model inv d_inverter (rise_delay=1e-5 fall_delay=1e-5) -* -adac [clk clk_bar] [3 4] dac -.model dac dac_bridge (t_rise=1e-5 t_fall=1e-5) -* -asum [1 2 3 4] 5 sum -.model sum summer -* -r3 3 0 1k -r4 4 0 1k -r5 5 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/mixed_mode.deck b/Windows/spice/examples/xspice/original-examples/mixed_mode.deck deleted file mode 100644 index bdf9ee23..00000000 --- a/Windows/spice/examples/xspice/original-examples/mixed_mode.deck +++ /dev/null @@ -1,98 +0,0 @@ -Mixed IO types -* -* This circuit contains a mixture of IO types, including -* analog, digital, user-defined (real), and 'null'. -* -* The circuit demonstrates the use of the digital and -* user-defined node capability to model system-level designs -* such as sampled-data filters. The simulated circuit -* contains a digital oscillator enabled after 100us. The -* square wave oscillator output is divided by 8 with a -* ripple counter. The result is passed through a digital -* filter to convert it to a sine wave. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 pulse(0 1 1e-4 1e-6) -r1 1 0 1k -* -abridge1 [1] [enable] atod -.model atod adc_bridge -* -aclk [enable clk] clk nand -.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5) -* -adiv2 div2_out clk NULL NULL NULL div2_out dff -adiv4 div4_out div2_out NULL NULL NULL div4_out dff -adiv8 div8_out div4_out NULL NULL NULL div8_out dff -.model dff d_dff -* -abridge2 div8_out enable filt_in node_bridge2 -.model node_bridge2 d_to_real (zero=-1 one=1) -* -xfilter filt_in clk filt_out dig_filter -* -abridge3 filt_out a_out node_bridge3 -.model node_bridge3 real_to_v -* -rlpf1 a_out oa_minus 10k -* -xlpf 0 oa_minus lpf_out opamp -* -rlpf2 oa_minus lpf_out 10k -clpf lpf_out oa_minus 0.01uF -* -* -.subckt dig_filter filt_in clk filt_out -* -.model n0 real_gain (gain=1.0) -.model n1 real_gain (gain=2.0) -.model n2 real_gain (gain=1.0) -.model g1 real_gain (gain=0.125) -.model zm1 real_delay -.model d0a real_gain (gain=-0.75) -.model d1a real_gain (gain=0.5625) -.model d0b real_gain (gain=-0.3438) -.model d1b real_gain (gain=1.0) -* -an0a filt_in x0a n0 -an1a filt_in x1a n1 -an2a filt_in x2a n2 -* -az0a x0a clk x1a zm1 -az1a x1a clk x2a zm1 -* -ad0a x2a x0a d0a -ad1a x2a x1a d1a -* -az2a x2a filt1_out g1 -az3a filt1_out clk filt2_in zm1 -* -an0b filt2_in x0b n0 -an1b filt2_in x1b n1 -an2b filt2_in x2b n2 -* -az0b x0b clk x1b zm1 -az1b x1b clk x2b zm1 -* -ad0 x2b x0b d0b -ad1 x2b x1b d1b -* -az2b x2b clk filt_out zm1 -* -.ends dig_filter -* -* -.subckt opamp plus minus out -* -r1 plus minus 300k -a1 %vd (plus minus) outint lim -.model lim limit (out_lower_limit = -12 out_upper_limit = 12 -+ fraction = true limit_range = 0.2 gain=300e3) -r3 outint out 50.0 -r2 out 0 1e12 -* -.ends opamp -* -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/mixed_ref.deck b/Windows/spice/examples/xspice/original-examples/mixed_ref.deck deleted file mode 100644 index 3dd3faad..00000000 --- a/Windows/spice/examples/xspice/original-examples/mixed_ref.deck +++ /dev/null @@ -1,41 +0,0 @@ -Mixed references -* -* This circuit demonstrates the use of single-ended and -* differential inputs and outputs. -* -* Note that digital models reference a single node for -* their inputs and output (i.e. they are single-ended) -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 5k) -v2 2 0 0.0 sin(0 1 1k) -* -r1 1 0 1k -r2 2 0 1k -* -* -a1 %v 1 %i 10 times10 -r10 10 0 1k -* -* -a2 %vd (1 2) %id(11 12) times10 -r11 11 0 1k -r12 12 0 1k -r11_12 11 12 1.0 -* -* -r3 2 3 1k -a3 %i 3 %v 13 times10 -r13 13 0 1k -* -a4 [1] [digital_node1] adc -.model adc adc_bridge -* -a5 digital_node1 digital_node2 inv -.model inv d_inverter -* -* -.model times10 gain (gain=10) -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/mosamp2.in b/Windows/spice/examples/xspice/original-examples/mosamp2.in deleted file mode 100644 index fff88e10..00000000 --- a/Windows/spice/examples/xspice/original-examples/mosamp2.in +++ /dev/null @@ -1,42 +0,0 @@ -mosamp2 - mos amplifier - transient -.options acct abstol=10n vntol=10n -.tran 0.1us 10us -m1 15 15 1 32 m w=88.9u l=25.4u -m2 1 1 2 32 m w=12.7u l=266.7u -m3 2 2 30 32 m w=88.9u l=25.4u -m4 15 5 4 32 m w=12.7u l=106.7u -m5 4 4 30 32 m w=88.9u l=12.7u -m6 15 15 5 32 m w=44.5u l=25.4u -m7 5 20 8 32 m w=482.6u l=12.7u -m8 8 2 30 32 m w=88.9u l=25.4u -m9 15 15 6 32 m w=44.5u l=25.4u -m10 6 21 8 32 m w=482.6u l=12.7u -m11 15 6 7 32 m w=12.7u l=106.7u -m12 7 4 30 32 m w=88.9u l=12.7u -m13 15 10 9 32 m w=139.7u l=12.7u -m14 9 11 30 32 m w=139.7u l=12.7u -m15 15 15 12 32 m w=12.7u l=207.8u -m16 12 12 11 32 m w=54.1u l=12.7u -m17 11 11 30 32 m w=54.1u l=12.7u -m18 15 15 10 32 m w=12.7u l=45.2u -m19 10 12 13 32 m w=270.5u l=12.7u -m20 13 7 30 32 m w=270.5u l=12.7u -m21 15 10 14 32 m w=254u l=12.7u -m22 14 11 30 32 m w=241.3u l=12.7u -m23 15 20 16 32 m w=19u l=38.1u -m24 16 14 30 32 m w=406.4u l=12.7u -m25 15 15 20 32 m w=38.1u l=42.7u -m26 20 16 30 32 m w=381u l=25.4u -m27 20 15 66 32 m w=22.9u l=7.6u -cc 7 9 40pf -cl 66 0 70pf -vin 21 0 pulse(0 5 1ns 1ns 1ns 5us 10us) -vccp 15 0 dc +15 -vddn 30 0 dc -15 -vb 32 0 dc -20 -.model m nmos(nsub=2.2e15 uo=575 ucrit=49k uexp=0.1 tox=0.11u xj=2.95u -+ level=2 cgso=1.5n cgdo=1.5n cbd=4.5f cbs=4.5f ld=2.4485u nss=3.2e10 -+ kp=2e-5 phi=0.6 ) -.print tran v(20) v(66) -.plot tran v(20) v(66) -.end diff --git a/Windows/spice/examples/xspice/original-examples/mosmem.in b/Windows/spice/examples/xspice/original-examples/mosmem.in deleted file mode 100644 index 2654ca8e..00000000 --- a/Windows/spice/examples/xspice/original-examples/mosmem.in +++ /dev/null @@ -1,27 +0,0 @@ -mosmem - mos memory cell -.width in=72 -.opt abstol=1u -.opt acct list node -.tran 20ns 2us -vdd 9 0 dc 5 -vs 7 0 pulse(2 0 520ns 20ns 20ns 500ns 2000ns) -vw 1 0 pulse(0 2 20ns 20ns 500ns 200ns) -vwb 2 0 pulse(2 0 20ns 20ns 20ns 2000ns 2000ns) -m1 3 1 0 0 mod w=250u l=5u -m2 4 2 0 0 mod w=250u l=5u -m3 9 9 3 0 mod w=5u l=5u -m4 9 9 4 0 mod w=5u l=5u -m5 5 7 3 0 mod w=50u l=5u -m6 6 7 4 0 mod w=50u l=5u -m7 5 6 0 0 mod w=250u l=5u -m8 6 5 0 0 mod w=250u l=5u -m9 9 9 5 0 mod w=5u l=5u -m10 9 9 6 0 mod w=5u l=5u -m11 8 4 0 0 mod w=250u l=5u -m12 9 9 8 0 mod w=5u l=5u -.model mod nmos(vto=0.5 phi=0.7 kp=1.0e-6 gamma=1.83 lambda=0.115 -+ level=1 cgso=1u cgdo=1u cbd=50p cbs=50p) -.print dc v(5) v(6) -.plot dc v(6) -.plot tran v(6) v(5) v(7) v(1) v(2) -.end diff --git a/Windows/spice/examples/xspice/original-examples/param_defaults.deck b/Windows/spice/examples/xspice/original-examples/param_defaults.deck deleted file mode 100644 index 3553fd0e..00000000 --- a/Windows/spice/examples/xspice/original-examples/param_defaults.deck +++ /dev/null @@ -1,16 +0,0 @@ -Parameter defaults -* -* This circuit contains a code model with -* parameters of various types, which are all defaulted, -* and prints the default values. -* -.op -* -r1 1 0 1k -r2 2 0 1k -r3 1 2 1k -* -a1 [1 2] mod -.model mod print_param_types -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/param_types.deck b/Windows/spice/examples/xspice/original-examples/param_types.deck deleted file mode 100644 index 31a0c754..00000000 --- a/Windows/spice/examples/xspice/original-examples/param_types.deck +++ /dev/null @@ -1,23 +0,0 @@ -Parameter types -* -* This circuit contains a code model which accepts several -* parameters of various types and prints them. -* -.op -* -r1 1 0 1k -r2 2 0 1k -r3 1 2 1k -* -a1 [1 2] mod -.model mod print_param_types -+ integer=2 -+ real=3.0 -+ complex=<4.0 5.0> -+ string=six -+ integer_array=[7 8] -+ real_array=[9.0 10.0] -+ complex_array=[< 11.0 12.0 > < 13.0 14.0 >] -+ string_array=[fifteen sixteen] -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/parsing.deck b/Windows/spice/examples/xspice/original-examples/parsing.deck deleted file mode 100644 index 1eb814a4..00000000 --- a/Windows/spice/examples/xspice/original-examples/parsing.deck +++ /dev/null @@ -1,16 +0,0 @@ -Parsing -* -* This circuit contains a simple gain block to demonstrate -* that the simulator parses the syntax used to reference -* code models. -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -r1 1 0 1k -* -a1 1 2 gain_block -.model gain_block gain (gain=10) -r2 2 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/polarity.deck b/Windows/spice/examples/xspice/original-examples/polarity.deck deleted file mode 100644 index 0724d814..00000000 --- a/Windows/spice/examples/xspice/original-examples/polarity.deck +++ /dev/null @@ -1,26 +0,0 @@ -Polarity of voltages and currents -* -* This circuit contains a set of gain blocks to evaluate -* the polarity of voltages and currents on code models -* -.tran 1e-5 1e-3 -* -v1 1 0 0.0 sin(0 1 1k) -* -r1 1 0 1k -* -* -a1 %v 1 %v 10 times10 -r10 10 0 1k -* -r1_2 1 2 1k -a2 %i 2 %v 11 times10 -r11 11 0 1k -* -a3 1 %i 12 times10 -r12 12 0 1k -* -* -.model times10 gain (gain=10) -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/rca3040.in b/Windows/spice/examples/xspice/original-examples/rca3040.in deleted file mode 100644 index 75eba090..00000000 --- a/Windows/spice/examples/xspice/original-examples/rca3040.in +++ /dev/null @@ -1,33 +0,0 @@ -rca3040 ckt - rca 3040 wideband amplifier -.ac dec 10 1 10ghz -.dc vin -0.25 0.25 0.005 -.tran 2.0ns 200ns -vin 1 0 sin(0 0.1 50meg 0.5ns) ac 1 -vcc 2 0 15.0 -vee 3 0 -15.0 -rs1 30 1 1k -rs2 31 0 1k -r1 5 3 4.8k -r2 6 3 4.8k -r3 9 3 811 -r4 8 3 2.17k -r5 8 0 820 -r6 2 14 1.32k -r7 2 12 4.5k -r8 2 15 1.32k -r9 16 0 5.25k -r10 17 0 5.25k -q1 2 30 5 qnl -q2 2 31 6 qnl -q3 10 5 7 qnl -q4 11 6 7 qnl -q5 14 12 10 qnl -q6 15 12 11 qnl -q7 12 12 13 qnl -q8 13 13 0 qnl -q9 7 8 9 qnl -q10 2 15 16 qnl -q11 2 14 17 qnl -.model qnl npn bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf -+ cjc=2pf va 50 -.end diff --git a/Windows/spice/examples/xspice/original-examples/rtlinv.in b/Windows/spice/examples/xspice/original-examples/rtlinv.in deleted file mode 100644 index ad7de749..00000000 --- a/Windows/spice/examples/xspice/original-examples/rtlinv.in +++ /dev/null @@ -1,20 +0,0 @@ -rtlinv ckt - cascaded rtl inverters -.width in=72 -.opt acct list node lvlcod=2 -.dc vin 0.0 2.5 0.025 -.tran 2ns 200ns -vcc 6 0 5 -vin 1 0 pulse(0 5 2ns 2ns 2ns 80ns) -rb1 1 2 10k -rc1 6 3 1k -q1 3 2 0 qnd -rb2 3 4 10k -q2 5 4 0 qnd -rc2 6 5 1k -.model qnd npn(bf=50 rb=70 rc=40 ccs=2pf tf=0.1ns tr=10ns cje=0.9pf -+ cjc=1.5pf pc=0.85 va=50) -.print dc v(3) v(5) -.plot dc v(3) -.print tran v(3) v(5) -.plot tran v(3) v(5) v(1) -.end diff --git a/Windows/spice/examples/xspice/original-examples/schmitt.in b/Windows/spice/examples/xspice/original-examples/schmitt.in deleted file mode 100644 index 49b08ebf..00000000 --- a/Windows/spice/examples/xspice/original-examples/schmitt.in +++ /dev/null @@ -1,24 +0,0 @@ -schmitt ckt - ecl compatible schmitt trigger -.width in=72 -.opt acct list node lvlcod=2 -.tran 10ns 1000ns -vin 1 0 pulse(-1.6 -1.2 10ns 400ns 400ns 100ns 10000ns) -vee 8 0 -5 -rin 1 2 50 -rc1 0 3 50 -r1 3 5 185 -r2 5 8 760 -rc2 0 6 100 -re 4 8 260 -rth1 7 8 125 -rth2 7 0 85 -cload 7 0 5pf -q1 3 2 4 qstd off -q2 6 5 4 qstd -q3 0 6 7 qstd -q4 0 6 7 qstd -.model qstd npn(is=1.0e-16 bf=50 br=0.1 rb=50 rc=10 tf=0.12ns tr=5ns -+ cje=0.4pf pe=0.8 me=0.4 cjc=0.5pf pc=0.8 mc=0.333 ccs=1pf va=50) -.print tran v(1) v(3) v(5) v(6) -.plot tran v(3) v(5) v(6) v(1) -.end diff --git a/Windows/spice/examples/xspice/original-examples/spice3.deck b/Windows/spice/examples/xspice/original-examples/spice3.deck deleted file mode 100644 index 0cd56b41..00000000 --- a/Windows/spice/examples/xspice/original-examples/spice3.deck +++ /dev/null @@ -1,25 +0,0 @@ -A Berkeley SPICE3 compatible circuit -* -* This circuit contains only Berkeley SPICE3 components. -* -* The circuit is an AC coupled transistor amplifier with -* a sinewave input at node "1", a gain of approximately -3.9, -* and output on node "coll". -* -.tran 1e-5 2e-3 -* -vcc vcc 0 12.0 -vin 1 0 0.0 ac 1.0 sin(0 1 1k) -* -ccouple 1 base 10uF -* -rbias1 vcc base 100k -rbias2 base 0 24k -* -q1 coll base emit generic -.model generic npn -* -rcollector vcc coll 3.9k -remitter emit 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/suffixes.deck b/Windows/spice/examples/xspice/original-examples/suffixes.deck deleted file mode 100644 index cbacf988..00000000 --- a/Windows/spice/examples/xspice/original-examples/suffixes.deck +++ /dev/null @@ -1,25 +0,0 @@ -Engineering suffixes -* -* This circuit contains a code model which accepts several -* parameters of various types and prints them. The values -* specified on the .model card use engineering suffixes on -* the numeric parameters. -* -.op -* -r1 1 0 1k -r2 2 0 1k -r3 1 2 1k -* -a1 [1 2] mod -.model mod print_param_types -+ integer=2k -+ real=3.0u -+ complex=< 4.0f 5.0mil > -+ string=six -+ integer_array=[7meg 8] -+ real_array=[9.0n 10.0p] -+ complex_array=[< 11.0t 12.0g > < 13.0m 14.0 >] -+ string_array=[fifteen sixteen] -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/supply_ramping.deck b/Windows/spice/examples/xspice/original-examples/supply_ramping.deck deleted file mode 100644 index beb3539e..00000000 --- a/Windows/spice/examples/xspice/original-examples/supply_ramping.deck +++ /dev/null @@ -1,30 +0,0 @@ -Supply ramping option -* -* This circuit demonstrates the use of the option -* "ramptime" which ramps independent sources and the -* capacitor and inductor initial conditions from -* zero to their final value during the time period -* specified. -* -* -.tran 0.1 5 -.option ramptime=0.2 -* -a1 1 0 cap -.model cap capacitor (c=1000uf ic=1) -r1 1 0 1k -* -a2 2 0 ind -.model ind inductor (l=1H ic=1) -r2 2 0 1.0 -* -v1 3 0 1.0 -r3 3 0 1k -* -i1 4 0 1e-3 -r4 4 0 1k -* -v2 5 0 0.0 sin(0 1 0.3 0 0 45.0) -r5 5 0 1k -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/user_defined_nodes.deck b/Windows/spice/examples/xspice/original-examples/user_defined_nodes.deck deleted file mode 100644 index 6a3c7236..00000000 --- a/Windows/spice/examples/xspice/original-examples/user_defined_nodes.deck +++ /dev/null @@ -1,30 +0,0 @@ -User defined nodes -* -* This circuit contains a mix of node types including -* two 'real' type user-defined nodes and associated -* node bridges. -* -.tran 1e-6 1e-4 -* -v1 1 0 0.0 pulse(0 1 2e-5) -r1 1 0 1k -* -abridge1 [1] [enable] node_bridge1 -.model node_bridge1 adc_bridge -* -aclk [enable clk] clk nand -.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5) -* -abridge2 clk enable real_node1 node_bridge2 -.model node_bridge2 d_to_real (zero=-1 one=1) -* -again real_node1 real_node2 times10 -.model times10 real_gain (gain=10) -* -abridge3 real_node2 analog_node node_bridge3 -.model node_bridge3 real_to_v -* -rout analog_node 0 1k -* -* -.end diff --git a/Windows/spice/examples/xspice/original-examples/xspice.deck b/Windows/spice/examples/xspice/original-examples/xspice.deck deleted file mode 100644 index b79ed4fe..00000000 --- a/Windows/spice/examples/xspice/original-examples/xspice.deck +++ /dev/null @@ -1,22 +0,0 @@ -A simple XSPICE amplifier circuit -* -* This uses an XSPICE "gain" code model to substitute for -* the transistor amplifier circuit in spice3.deck. -* -.tran 1e-5 2e-3 -* -vin 1 0 0.0 ac 1.0 sin(0 1 1k) -* -ccouple 1 in 10uF -* -* -rzin in 0 19.35k -* -aamp in coll gain_block -.model gain_block gain (gain = -3.9 out_offset = 7.003) -* -rzout out coll 3.9k -rbig coll 0 1e12 -* -* -.end |