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| author | rahulp13 | 2020-02-28 11:38:58 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-28 11:38:58 +0530 |
| commit | 246319682f60293b132fca1ce6e24689c6682617 (patch) | |
| tree | 6871b758a17869efecfd617f5513e31f9a933f4a /Windows/spice/examples/xspice/fstest.sp | |
| parent | d9ab84106cac311d953f344386fef1c1e2bca1cf (diff) | |
| download | eSim-246319682f60293b132fca1ce6e24689c6682617.tar.gz eSim-246319682f60293b132fca1ce6e24689c6682617.tar.bz2 eSim-246319682f60293b132fca1ce6e24689c6682617.zip | |
initial commit
Diffstat (limited to 'Windows/spice/examples/xspice/fstest.sp')
| -rw-r--r-- | Windows/spice/examples/xspice/fstest.sp | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Windows/spice/examples/xspice/fstest.sp b/Windows/spice/examples/xspice/fstest.sp new file mode 100644 index 00000000..f0f552a8 --- /dev/null +++ b/Windows/spice/examples/xspice/fstest.sp @@ -0,0 +1,26 @@ +* filesource Test + +* two differential ports 1 0 and 3 0 are used, so your input file +* has to have three columns (time, port_value 1, portvalue 2) + +AFILESRC %vd([1 0 3 0]) filesrc +.model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1] timerelative=false amplstep=false) + +V2 2 0 0.0 SIN(0 1 1MEG 0 0 0.0) +V4 4 0 0.0 SIN(0 1 1MEG 0 0 90.0) + +.tran 1n 1.0u + +.control +run +*listing param +wrdata vspice V(1) V(2) V(3) V(4) + + +plot V(1) V(2) V(3) V(4) + +* error between interpolation and sine source +* should be less than 1mV up to 1us +plot V(1,2) V(3,4) +.endc +.end |