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| author | rahulp13 | 2020-03-03 05:31:58 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-03-03 05:31:58 +0530 |
| commit | dfc268e0863c913a1b8726cd54eea3b40caf7c67 (patch) | |
| tree | 1cd82634684da5ae86b558d44756189e080545d4 /Windows/spice/examples/vdmos/inv_vdmos.cir | |
| parent | fd62c52150c7d1f81da8060b2f5db6b94d174ccf (diff) | |
| download | eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.gz eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.bz2 eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.zip | |
upgrade ngspice to v31
Diffstat (limited to 'Windows/spice/examples/vdmos/inv_vdmos.cir')
| -rw-r--r-- | Windows/spice/examples/vdmos/inv_vdmos.cir | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/Windows/spice/examples/vdmos/inv_vdmos.cir b/Windows/spice/examples/vdmos/inv_vdmos.cir new file mode 100644 index 00000000..1fa247c8 --- /dev/null +++ b/Windows/spice/examples/vdmos/inv_vdmos.cir @@ -0,0 +1,24 @@ +*****************==== Inverter ====******************* +*********** VDMOS **************************** +vdd 1 0 5 + +.subckt inv out in vdd vss +mp1 out in vdd p1 +mn1 out in vss n1 +.ends + +xinv 3 2 1 0 inv + +Vin 2 0 Pulse (0 5 10n 10n 10n 140n 300n) + +.tran 1n 1u + +.control +run +* current and output in a single plot +plot v(2) v(3) +.endc + +.model N1 vdmos cgdmin=0.2p cgdmax=1p a=2 cgs=0.5p rg=5k rb=1e9 cjo=0.1p +.model P1 vdmos cgdmin=0.2p cgdmax=1p a=2 cgs=0.5p rg=5k rb=1e9 cjo=0.1p pchan +.end |