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| author | rahulp13 | 2020-03-03 05:31:58 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-03-03 05:31:58 +0530 |
| commit | dfc268e0863c913a1b8726cd54eea3b40caf7c67 (patch) | |
| tree | 1cd82634684da5ae86b558d44756189e080545d4 /Windows/spice/examples/soi/inv_tr.sp | |
| parent | fd62c52150c7d1f81da8060b2f5db6b94d174ccf (diff) | |
| download | eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.gz eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.tar.bz2 eSim-dfc268e0863c913a1b8726cd54eea3b40caf7c67.zip | |
upgrade ngspice to v31
Diffstat (limited to 'Windows/spice/examples/soi/inv_tr.sp')
| -rw-r--r-- | Windows/spice/examples/soi/inv_tr.sp | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/Windows/spice/examples/soi/inv_tr.sp b/Windows/spice/examples/soi/inv_tr.sp new file mode 100644 index 00000000..b486374b --- /dev/null +++ b/Windows/spice/examples/soi/inv_tr.sp @@ -0,0 +1,32 @@ +SOI Inverter +* Mx Drain Gate Source Back-gate(substrate) Body Tx W L (body ommitted for FB) + +.include ./bsim4soi/nmos4p0.mod +.include ./bsim4soi/pmos4p0.mod +.option TEMP=27C + +Vpower VD 0 1.5 +Vgnd VS 0 0 + +Vgate Gate VS DC 0 PULSE(0v 1.5v 100ps 50ps 50ps 200ps 500ps) + +*MN0 Out Gate VS VS VS N1 W=10u L=0.18u debug=1 +*MP0 Out Gate VD VS VD P1 W=20u L=0.18u debug=1 + +MN0 Out Gate VS VS N1 W=10u L=0.18u Pd=11u Ps=11u +MP0 Out Gate VD VS P1 W=20u L=0.18u Pd=11u Ps=11u + +.tran 3p 600ps +.print tran v(gate) v(out) + +.control +if $?batchmode +* do nothing +else + run + plot Vgnd#branch + plot gate out +endif +.endc + +.END |