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authorrahulp132021-01-07 18:22:29 +0530
committerrahulp132021-01-07 18:22:29 +0530
commitd4fd47ecf77597595d3f4fa72fd5334a5fe7417b (patch)
tree28095229ec3035d15c569fbedac83cf5876aa196 /Windows/spice/examples/soi/inv_tr.sp
parent376e748df438933088721286402462dffd6367c0 (diff)
parent63e3156454f39732a3101c29d42b473a89ca68d2 (diff)
downloadeSim-d4fd47ecf77597595d3f4fa72fd5334a5fe7417b.tar.gz
eSim-d4fd47ecf77597595d3f4fa72fd5334a5fe7417b.tar.bz2
eSim-d4fd47ecf77597595d3f4fa72fd5334a5fe7417b.zip
Merge windows installer updates with linux installer
Diffstat (limited to 'Windows/spice/examples/soi/inv_tr.sp')
-rw-r--r--Windows/spice/examples/soi/inv_tr.sp32
1 files changed, 0 insertions, 32 deletions
diff --git a/Windows/spice/examples/soi/inv_tr.sp b/Windows/spice/examples/soi/inv_tr.sp
deleted file mode 100644
index b486374b..00000000
--- a/Windows/spice/examples/soi/inv_tr.sp
+++ /dev/null
@@ -1,32 +0,0 @@
-SOI Inverter
-* Mx Drain Gate Source Back-gate(substrate) Body Tx W L (body ommitted for FB)
-
-.include ./bsim4soi/nmos4p0.mod
-.include ./bsim4soi/pmos4p0.mod
-.option TEMP=27C
-
-Vpower VD 0 1.5
-Vgnd VS 0 0
-
-Vgate Gate VS DC 0 PULSE(0v 1.5v 100ps 50ps 50ps 200ps 500ps)
-
-*MN0 Out Gate VS VS VS N1 W=10u L=0.18u debug=1
-*MP0 Out Gate VD VS VD P1 W=20u L=0.18u debug=1
-
-MN0 Out Gate VS VS N1 W=10u L=0.18u Pd=11u Ps=11u
-MP0 Out Gate VD VS P1 W=20u L=0.18u Pd=11u Ps=11u
-
-.tran 3p 600ps
-.print tran v(gate) v(out)
-
-.control
-if $?batchmode
-* do nothing
-else
- run
- plot Vgnd#branch
- plot gate out
-endif
-.endc
-
-.END