diff options
| author | rahulp13 | 2020-02-28 11:38:58 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-28 11:38:58 +0530 |
| commit | 246319682f60293b132fca1ce6e24689c6682617 (patch) | |
| tree | 6871b758a17869efecfd617f5513e31f9a933f4a /Windows/spice/examples/snapshot/adder_mos_circ.cir | |
| parent | d9ab84106cac311d953f344386fef1c1e2bca1cf (diff) | |
| download | eSim-246319682f60293b132fca1ce6e24689c6682617.tar.gz eSim-246319682f60293b132fca1ce6e24689c6682617.tar.bz2 eSim-246319682f60293b132fca1ce6e24689c6682617.zip | |
initial commit
Diffstat (limited to 'Windows/spice/examples/snapshot/adder_mos_circ.cir')
| -rw-r--r-- | Windows/spice/examples/snapshot/adder_mos_circ.cir | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/Windows/spice/examples/snapshot/adder_mos_circ.cir b/Windows/spice/examples/snapshot/adder_mos_circ.cir new file mode 100644 index 00000000..b0a591e4 --- /dev/null +++ b/Windows/spice/examples/snapshot/adder_mos_circ.cir @@ -0,0 +1,61 @@ +* ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER + +*** SUBCIRCUIT DEFINITIONS +.SUBCKT NAND in1 in2 out VDD +* NODES: INPUT(2), OUTPUT, VCC +M1 out in2 Vdd Vdd p1 W=3u L=1u +M2 net.1 in2 0 0 n1 W=3u L=2u +M3 out in1 Vdd Vdd p1 W=3u L=1u +M4 out in1 net.1 0 n1 W=3u L=2u +.ENDS NAND + +.SUBCKT ONEBIT 1 2 3 4 5 6 +* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC +X1 1 2 7 6 NAND +X2 1 7 8 6 NAND +X3 2 7 9 6 NAND +X4 8 9 10 6 NAND +X5 3 10 11 6 NAND +X6 3 11 12 6 NAND +X7 10 11 13 6 NAND +X8 12 13 4 6 NAND +X9 11 7 5 6 NAND +.ENDS ONEBIT + +.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 +* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, +* CARRY-IN, CARRY-OUT, VCC +X1 1 2 7 5 10 9 ONEBIT +X2 3 4 10 6 8 9 ONEBIT +.ENDS TWOBIT + +.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), +* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC +X1 1 2 3 4 9 10 13 16 15 TWOBIT +X2 5 6 7 8 11 12 16 14 15 TWOBIT +.ENDS FOURBIT + +*** DEFINE NOMINAL CIRCUIT +VCC 99 0 DC 3.3V +VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS) +VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS) +VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS) +VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS) +VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS) +VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS) +VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS) +VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS) +X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT +*RBIT0 9 0 100K +*RBIT1 10 0 100K +*RBIT2 11 0 100K +*RBIT3 12 0 100K +*RCOUT 13 0 100K + +.TRAN 1NS 1000NS + +.model n1 nmos level=8 version=3.3.0 +.model p1 pmos level=8 version=3.3.0 + +.END |