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| author | Rahul Paknikar | 2021-01-08 12:47:23 +0530 |
|---|---|---|
| committer | GitHub | 2021-01-08 12:47:23 +0530 |
| commit | e6f48f5b1bf22a1d048b44ed4416b4315a461306 (patch) | |
| tree | fd357549a236cdc652f0b6d2919beee0cee7faa5 /Windows/spice/examples/cider/resistor | |
| parent | ac223c4a69c701ad0a247401acdc48b8b6b6dba6 (diff) | |
| parent | 6b512cbf954273b0f21d3800d10a7ad42a759425 (diff) | |
| download | eSim-e6f48f5b1bf22a1d048b44ed4416b4315a461306.tar.gz eSim-e6f48f5b1bf22a1d048b44ed4416b4315a461306.tar.bz2 eSim-e6f48f5b1bf22a1d048b44ed4416b4315a461306.zip | |
Merge pull request #161 from rahulp13/installersi2.1
fixed key issue for ubuntu 20+; updated installers for windows os
Diffstat (limited to 'Windows/spice/examples/cider/resistor')
| -rw-r--r-- | Windows/spice/examples/cider/resistor/gaasres.cir | 30 | ||||
| -rw-r--r-- | Windows/spice/examples/cider/resistor/sires.cir | 26 |
2 files changed, 0 insertions, 56 deletions
diff --git a/Windows/spice/examples/cider/resistor/gaasres.cir b/Windows/spice/examples/cider/resistor/gaasres.cir deleted file mode 100644 index c35d0ddc..00000000 --- a/Windows/spice/examples/cider/resistor/gaasres.cir +++ /dev/null @@ -1,30 +0,0 @@ -Gallium Arsenide Resistor - -* This transient simulation demonstrates the effects of velocity overshoot -* and velocity saturation at high lateral electric fields. -* Do not try to do DC analysis of this resistor. It will not converge -* because of the peculiar characteristics of the GaAs velocity-field -* relation. In some cases, problems can arise in transient simulation -* as well. - -VPP 1 0 1v PWL 0s 0.0v 10s 1v -VNN 2 0 0.0v -D1 1 2 M_RES AREA=1 - -.MODEL M_RES numd level=1 -+ options resistor defa=1p -+ x.mesh loc=0.0 num=1 -+ x.mesh loc=1.0 num=101 -+ domain num=1 material=1 -+ material num=1 gaas -+ doping unif n.type conc=2.5e16 -+ models fieldmob srh auger conctau -+ method ac=direct - -*.OP -*.DC VPP 0.0v 10.01v 0.1v -.TRAN 1s 10.001s 0s 0.1s -.PRINT I(VPP) - -.OPTION ACCT BYPASS=1 -.END diff --git a/Windows/spice/examples/cider/resistor/sires.cir b/Windows/spice/examples/cider/resistor/sires.cir deleted file mode 100644 index 45e2aa12..00000000 --- a/Windows/spice/examples/cider/resistor/sires.cir +++ /dev/null @@ -1,26 +0,0 @@ -Silicon Resistor - -* This simulation demonstrates the effects of velocity saturation at -* high lateral electric fields. - -VPP 1 0 10v PWL 0s 0.0v 100s 10v -VNN 2 0 0.0v -D1 1 2 M_RES AREA=1 - -.MODEL M_RES numd level=1 -+ options resistor defa=1p -+ x.mesh loc=0.0 num=1 -+ x.mesh loc=1.0 num=101 -+ domain num=1 material=1 -+ material num=1 silicon -+ doping unif n.type conc=2.5e16 -+ models bgn srh conctau auger concmob fieldmob -+ method ac=direct - -*.OP -.DC VPP 0.0v 10.01v 0.1v -*.TRAN 1s 100.001s 0s 0.2s -.PRINT I(VPP) - -.OPTION ACCT BYPASS=1 RELTOL=1e-12 -.END |